| /llvm-project-15.0.7/llvm/include/llvm/ADT/ |
| H A D | SparseBitVector.h | 240 void intersectWithComplement(const SparseBitVectorElement &RHS1, in intersectWithComplement()
247 Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i]; in intersectWithComplement()
688 void intersectWithComplement(const SparseBitVector<ElementSize> &RHS1, in intersectWithComplement() argument
691 if (this == &RHS1) { in intersectWithComplement()
696 intersectWithComplement(RHS1, RHS2Copy); in intersectWithComplement()
702 ElementListConstIter Iter1 = RHS1.Elements.begin(); in intersectWithComplement()
707 if (RHS1.Elements.empty()) in intersectWithComplement()
712 if (Iter1 == RHS1.Elements.end()) in intersectWithComplement()
731 std::copy(Iter1, RHS1.Elements.end(), std::back_inserter(Elements)); in intersectWithComplement()
734 void intersectWithComplement(const SparseBitVector<ElementSize> *RHS1, in intersectWithComplement() argument
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 1211 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); in foldLogicOfFCmps() local
1214 if (LHS0 == RHS1 && RHS0 == LHS1) { in foldLogicOfFCmps()
1217 std::swap(RHS0, RHS1); in foldLogicOfFCmps()
1234 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldLogicOfFCmps()
2529 Value *LHS1 = LHS->getOperand(1), *RHS1 = RHS->getOperand(1); in foldAndOrOfICmps() local
2532 match(RHS1, m_APInt(RHSC)); in foldAndOrOfICmps()
2537 if (LHS0 == RHS1 && LHS1 == RHS0) { in foldAndOrOfICmps()
2541 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldAndOrOfICmps()
3190 if (LHS0 == RHS1 && LHS1 == RHS0) { in foldXorOfICmps()
3194 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldXorOfICmps()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | GuardWidening.cpp | 509 ConstantInt *RHS0, *RHS1; in widenCondCommon() local
513 match(Cond1, m_ICmp(Pred1, m_Specific(LHS), m_ConstantInt(RHS1)))) { in widenCondCommon()
520 ConstantRange::makeExactICmpRegion(Pred1, RHS1->getValue()); in widenCondCommon()
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| /llvm-project-15.0.7/mlir/test/Interfaces/TilingInterface/ |
| H A D | tile-and-fuse-using-interface.mlir | 107 // CHECK-SAME: %[[RHS1:[a-zA-Z0-9]+]]: tensor<?x?xf32>)
113 // CHECK-DAG: %[[D2:.+]] = tensor.dim %[[RHS1]], %[[C1]]
125 // CHECK-DAG: %[[RHS1_TILE:.+]] = tensor.extract_slice %[[RHS1]][0, 0]
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 1947 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); in simplifyAndOrOfFCmps() local
1962 if ((isKnownNeverNaN(LHS0, TLI) && (LHS1 == RHS0 || LHS1 == RHS1)) || in simplifyAndOrOfFCmps()
1963 (isKnownNeverNaN(LHS1, TLI) && (LHS0 == RHS0 || LHS0 == RHS1))) in simplifyAndOrOfFCmps()
1974 if ((isKnownNeverNaN(RHS0, TLI) && (RHS1 == LHS0 || RHS1 == LHS1)) || in simplifyAndOrOfFCmps()
1975 (isKnownNeverNaN(RHS1, TLI) && (RHS0 == LHS0 || RHS0 == LHS1))) in simplifyAndOrOfFCmps()
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| H A D | ValueTracking.cpp | 6805 const Value *RHS1, *RHS2; in isImpliedCondition() local
6806 if (match(RHS, m_LogicalOr(m_Value(RHS1), m_Value(RHS2)))) { in isImpliedCondition()
6808 isImpliedCondition(LHS, RHS1, DL, LHSIsTrue, Depth + 1)) in isImpliedCondition()
6816 if (match(RHS, m_LogicalAnd(m_Value(RHS1), m_Value(RHS2)))) { in isImpliedCondition()
6818 isImpliedCondition(LHS, RHS1, DL, LHSIsTrue, Depth + 1)) in isImpliedCondition()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 734 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, in getAVRCmp() local
748 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp); in getAVRCmp()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5639 SDValue RHS1, RHS2; in OptimizeVFPBrcond() local
5641 expandf64Toi32(RHS, DAG, RHS1, RHS2); in OptimizeVFPBrcond()
5647 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
12004 Register RHS1 = MI.getOperand(3).getReg(); in EmitInstrWithCustomInserter() local
12008 .addReg(RHS1) in EmitInstrWithCustomInserter()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 24151 SDValue RHS1, RHS2; in splitIntVSETCC() local
24152 std::tie(RHS1, RHS2) = splitVector(RHS, DAG, dl); in splitIntVSETCC()
24158 DAG.getNode(ISD::SETCC, dl, LoVT, LHS1, RHS1, CC), in splitIntVSETCC()
47028 SDValue RHS1 = RHS.getOperand(1); in combineVectorHADDSUB() local
47030 (RHS0 == RHS1 || RHS0.isUndef() || RHS1.isUndef())) { in combineVectorHADDSUB()
47034 RHS0.isUndef() ? RHS1 : RHS0); in combineVectorHADDSUB()
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