| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonEarlyIfConv.cpp | 131 unsigned PredR = 0; member
200 unsigned PredR, bool IfTrue);
253 Register PredR = T1I->getOperand(0).getReg(); in matchFlowPattern() local
334 FP = FlowPattern(B, PredR, TB, FB, JB); in matchFlowPattern()
711 unsigned PredR, bool IfTrue) { in predicateInstr() argument
729 MIB.addReg(PredR); in predicateInstr()
745 .addReg(PredR) in predicateInstr()
762 unsigned PredR, bool IfTrue) { in predicateBlockNB() argument
804 .addReg(PredR) in buildMux()
916 .addReg(FP.PredR) in convert()
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| H A D | HexagonGenMux.cpp | 92 unsigned PredR = 0; member
108 unsigned DefR, PredR; member
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
252 if (F != CM.end() && F->second.PredR != PR) { in genMuxInBlock()
259 F->second.PredR = PR; in genMuxInBlock()
340 .addReg(MX.PredR) in genMuxInBlock()
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| H A D | HexagonExpandCondsets.cpp | 223 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
230 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
747 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) { in getReachingDefForPred() argument
770 if (RR.Reg == PredR) { in getReachingDefForPred()
910 unsigned PredR, bool Cond, MachineBasicBlock::iterator First, in renameInRange() argument
919 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI))) in renameInRange()
959 Register PredR = MP.getReg(); in predicate() local
960 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond); in predicate()
977 if (!I->modifiesRegister(PredR, nullptr)) in predicate()
990 if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR)) in predicate()
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| H A D | HexagonHardwareLoops.cpp | 462 unsigned PredR, PredPos, PredRegFlags; in findInductionRegister() local
463 if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags)) in findInductionRegister()
466 MachineInstr *PredI = MRI->getVRegDef(PredR); in findInductionRegister()
1332 Register PredR = CmpI->getOperand(0).getReg(); in orderBumpCompare() local
1340 if (MO.getReg() == PredR) // Found an intervening use of PredR. in orderBumpCompare()
1897 Register PredR = PN->getOperand(i).getReg(); in createPreheaderForLoop() local
1903 MachineOperand MO = MachineOperand::CreateReg(PredR, false); in createPreheaderForLoop()
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| H A D | HexagonISelLowering.cpp | 378 Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); in LowerCallResult() local
379 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR, in LowerCallResult()
385 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1); in LowerCallResult()
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 242 ICmpInst::Predicate &PredR) { in getMaskedTypeForICmpPair() argument
318 if (!ICmpInst::isEquality(PredR)) in getMaskedTypeForICmpPair()
395 if (PredR != NewCC) in foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed()
509 PredL, PredR, Builder)) { in foldLogOpOfMaskedICmpsAsymmetric()
515 PredR, PredL, Builder)) { in foldLogOpOfMaskedICmpsAsymmetric()
1216 PredR = FCmpInst::getSwappedPredicate(PredR); in foldLogicOfFCmps()
1236 unsigned FCmpCodeR = getFCmpCode(PredR); in foldLogicOfFCmps()
2536 if (predicatesFoldable(PredL, PredR)) { in foldAndOrOfICmps()
2668 isSignBitCheck(PredR, *RHSC, TrueIfSignedR) && in foldAndOrOfICmps()
3189 if (predicatesFoldable(PredL, PredR)) { in foldXorOfICmps()
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| /llvm-project-15.0.7/polly/lib/Analysis/ |
| H A D | ScopBuilder.cpp | 708 auto *PredR = RI.getRegionFor(PredBB); in getPredecessorDomainConstraints() local
709 while (PredR->getExit() != BB && !PredR->contains(BB)) in getPredecessorDomainConstraints()
710 PredR = PredR->getParent(); in getPredecessorDomainConstraints()
714 if (PredR->getExit() == BB) { in getPredecessorDomainConstraints()
715 PredBB = PredR->getEntry(); in getPredecessorDomainConstraints()
716 PropagatedRegions.insert(PredR); in getPredecessorDomainConstraints()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | EarlyCSE.cpp | 411 CmpInst::Predicate PredL, PredR; in isEqualImpl() local
414 match(CondR, m_Cmp(PredR, m_Specific(X), m_Specific(Y))) && in isEqualImpl()
415 CmpInst::getInversePredicate(PredL) == PredR) in isEqualImpl()
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 1951 FCmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate(); in simplifyAndOrOfFCmps() local
1952 if ((PredL == FCmpInst::FCMP_ORD && PredR == FCmpInst::FCMP_ORD && IsAnd) || in simplifyAndOrOfFCmps()
1953 (PredL == FCmpInst::FCMP_UNO && PredR == FCmpInst::FCMP_UNO && !IsAnd)) { in simplifyAndOrOfFCmps()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/ |
| H A D | LoopVectorize.cpp | 8405 auto *PredR = dyn_cast_or_null<VPPredInstPHIRecipe>(Op->getDef()); in handleReplication() local
8406 if (!PredR) in handleReplication()
8409 cast_or_null<VPReplicateRecipe>(PredR->getOperand(0)->getDef()); in handleReplication()
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