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Searched refs:PhysReg (Results 1 – 25 of 101) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DReachingDefAnalysis.cpp286 return hasLocalDefBefore(MI, PhysReg) in getReachingLocalMIDef()
298 return getReachingDef(A, PhysReg) == getReachingDef(B, PhysReg); in hasSameReachingDef()
328 return getReachingDef(MI, PhysReg) >= 0; in hasLocalDefBefore()
409 getLiveOuts(MBB, PhysReg, Defs); in getGlobalReachingDefs()
448 getLiveOuts(Pred, PhysReg, Incoming); in getUniqueReachingMIDef()
496 getReachingDef(MI, PhysReg) != getReachingDef(&*Last, PhysReg)) in isRegDefinedAfter()
514 int Def = getReachingDef(MI, PhysReg); in isReachingDefLiveOut()
668 getGlobalUses(Def, PhysReg, Uses); in collectKilledOperands()
690 if (isRegUsedAfter(MI, PhysReg)) { in isSafeToDefRegAt()
693 getGlobalUses(Def, PhysReg, Uses); in isSafeToDefRegAt()
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H A DLiveRegMatrix.cpp106 << printReg(PhysReg, TRI) << ':'); in assign()
108 VRM->assignVirt2Phys(VirtReg.reg(), PhysReg); in assign()
122 Register PhysReg = VRM->getPhys(VirtReg.reg()); in unassign() local
127 foreachUnit(TRI, VirtReg, PhysReg, in unassign()
161 return !RegMaskUsable.empty() && (!PhysReg || !RegMaskUsable.test(PhysReg)); in checkRegMaskInterference()
168 CoalescerPair CP(VirtReg.reg(), PhysReg, *TRI); in checkRegUnitInterference()
187 MCRegister PhysReg) { in checkInterference() argument
192 if (checkRegMaskInterference(VirtReg, PhysReg)) in checkInterference()
196 if (checkRegUnitInterference(VirtReg, PhysReg)) in checkInterference()
200 bool Interference = foreachUnit(TRI, VirtReg, PhysReg, in checkInterference()
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H A DRegAllocFast.cpp543 MCPhysReg PhysReg = LR.PhysReg; in reloadAtBegin() local
704 LR.PhysReg = PhysReg; in assignVirtToPhysReg()
815 if (PhysReg == Hint0 || PhysReg == Hint1) in allocVirtReg()
833 LR.PhysReg = 0; in allocVirtReg()
847 MCPhysReg PhysReg; in allocVirtRegUndef() local
849 PhysReg = LRI->PhysReg; in allocVirtRegUndef()
859 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
927 MCPhysReg PhysReg = LRI->PhysReg; in defineVirtReg() local
1068 MCPhysReg PhysReg = LR.PhysReg; in dumpState() local
1315 MCPhysReg PhysReg = LR.PhysReg; in allocateInstruction() local
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H A DRegAllocGreedy.cpp368 MCRegister PhysReg; in tryAssign() local
375 PhysReg = *I; in tryAssign()
379 return PhysReg; in tryAssign()
405 return PhysReg; in tryAssign()
435 PhysReg = *I; in canReassign()
437 if (PhysReg) in canReassign()
441 return PhysReg; in canReassign()
1933 if (PhysReg == ~0u || (!PhysReg && !LI->empty())) in tryRecoloringCandidates()
1936 if (!PhysReg) { in tryRecoloringCandidates()
2018 return PhysReg; in tryAssignCSRFirstTime()
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H A DRegAllocBasic.cpp209 MCRegister PhysReg, in spillInterferences() argument
224 LLVM_DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI) in spillInterferences()
267 for (MCRegister PhysReg : Order) { in selectOrSplit() local
268 assert(PhysReg.isValid()); in selectOrSplit()
270 switch (Matrix->checkInterference(VirtReg, PhysReg)) { in selectOrSplit()
273 return PhysReg; in selectOrSplit()
277 PhysRegSpillCands.push_back(PhysReg); in selectOrSplit()
287 for (MCRegister &PhysReg : PhysRegSpillCands) { in selectOrSplit()
288 if (!spillInterferences(VirtReg, PhysReg, SplitVRegs)) in selectOrSplit()
291 assert(!Matrix->checkInterference(VirtReg, PhysReg) && in selectOrSplit()
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H A DRegisterClassInfo.cpp125 for (unsigned PhysReg : RawOrder) { in compute() local
127 if (Reserved.test(PhysReg)) in compute()
129 uint8_t Cost = RegCosts[PhysReg]; in compute()
132 if (CalleeSavedAliases[PhysReg] && in compute()
133 !STI.ignoreCSRForAllocationOrder(*MF, PhysReg)) in compute()
135 CSRAlias.push_back(PhysReg); in compute()
139 RCI.Order[N++] = PhysReg; in compute()
148 unsigned PhysReg = CSRAlias[i]; in compute() local
149 uint8_t Cost = RegCosts[PhysReg]; in compute()
152 RCI.Order[N++] = PhysReg; in compute()
H A DVirtRegMap.cpp334 MBB->addLiveIn(PhysReg, LaneMask); in addLiveInsForSubRanges()
350 Register PhysReg = VRM->getPhys(VirtReg); in addMBBLiveIns() local
351 if (PhysReg == VirtRegMap::NO_PHYS_REG) { in addMBBLiveIns()
359 addLiveInsForSubRanges(LI, PhysReg); in addMBBLiveIns()
369 MBB->addLiveIn(PhysReg); in addMBBLiveIns()
559 RewriteRegs.insert(PhysReg); in rewrite()
571 SuperKills.push_back(PhysReg); in rewrite()
578 SuperDefs.push_back(PhysReg); in rewrite()
602 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewrite()
608 MO.setReg(PhysReg); in rewrite()
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H A DRegAllocEvictionAdvisor.cpp168 const LiveInterval &VirtReg, MCRegister PhysReg, in canEvictHintInterference() argument
172 return canEvictInterferenceBasedOnCost(VirtReg, PhysReg, true, MaxCost, in canEvictHintInterference()
186 const LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint, in canEvictInterferenceBasedOnCost() argument
189 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg) in canEvictInterferenceBasedOnCost()
204 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in canEvictInterferenceBasedOnCost()
266 (!EnableLocalReassign || !canReassign(*Intf, PhysReg))) { in canEvictInterferenceBasedOnCost()
296 MCRegister PhysReg = *I; in tryFindEvictionCandidate() local
297 assert(PhysReg); in tryFindEvictionCandidate()
298 if (!canAllocatePhysReg(CostPerUseLimit, PhysReg) || in tryFindEvictionCandidate()
299 !canEvictInterferenceBasedOnCost(VirtReg, PhysReg, false, BestCost, in tryFindEvictionCandidate()
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H A DInterferenceCache.h47 MCRegister PhysReg = 0; variable
105 PhysReg = MCRegister::NoRegister; in clear()
111 MCRegister getPhysReg() const { return PhysReg; } in getPhysReg()
155 Entry *get(MCRegister PhysReg);
208 void setPhysReg(InterferenceCache &Cache, MCRegister PhysReg) { in setPhysReg() argument
212 if (PhysReg.isValid()) in setPhysReg()
213 setEntry(Cache.get(PhysReg)); in setPhysReg()
H A DInterferenceCache.cpp63 InterferenceCache::Entry *InterferenceCache::get(MCRegister PhysReg) { in get() argument
64 unsigned char E = PhysRegEntries[PhysReg.id()]; in get()
65 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) { in get()
81 Entries[E].reset(PhysReg, LIUArray, TRI, MF); in get()
82 PhysRegEntries[PhysReg] = E; in get()
96 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) in revalidate()
107 PhysReg = physReg; in reset()
113 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in reset()
122 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) { in valid()
194 if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) { in update()
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H A DRegAllocGreedy.h216 MCRegister PhysReg; member
229 PhysReg = Reg; in reset()
329 bool mayRecolorAllInterferences(MCRegister PhysReg,
352 AllocationOrder &Order, MCRegister PhysReg,
381 MCRegister PhysReg; member
383 HintInfo(BlockFrequency Freq, Register Reg, MCRegister PhysReg) in HintInfo()
384 : Freq(Freq), Reg(Reg), PhysReg(PhysReg) {} in HintInfo()
H A DMLRegallocEvictAdvisor.cpp295 const LiveInterval &VirtReg, MCRegister PhysReg, in canEvictHintInterference() argument
297 return getDefaultAdvisor().canEvictHintInterference(VirtReg, PhysReg, in canEvictHintInterference()
530 const LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint, in loadInterferenceFeatures() argument
547 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in loadInterferenceFeatures()
639 MCRegister PhysReg = *I; in tryFindEvictionCandidate() local
641 assert(PhysReg); in tryFindEvictionCandidate()
642 if (!canAllocatePhysReg(CostPerUseLimit, PhysReg)) { in tryFindEvictionCandidate()
648 Regs[Pos] = std::make_pair(PhysReg, true); in tryFindEvictionCandidate()
854 MCRegister PhysReg = getDefaultAdvisor().tryFindEvictionCandidate( in tryFindEvictionCandidatePosition() local
859 if (!PhysReg) in tryFindEvictionCandidatePosition()
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H A DMachineRegisterInfo.cpp509 bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { in isConstantPhysReg()
510 assert(Register::isPhysicalRegister(PhysReg)); in isConstantPhysReg()
513 if (TRI->isConstantPhysReg(PhysReg)) in isConstantPhysReg()
518 for (MCRegAliasIterator AI(PhysReg, TRI, true); in isConstantPhysReg()
566 bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg, in isPhysRegModified() argument
568 if (UsedPhysRegMask.test(PhysReg)) in isPhysRegModified()
571 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) { in isPhysRegModified()
581 bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg, in isPhysRegUsed() argument
583 if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg)) in isPhysRegUsed()
586 for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid(); in isPhysRegUsed()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DReachingDefAnalysis.h142 int getReachingDef(MachineInstr *MI, MCRegister PhysReg) const;
146 MCRegister PhysReg) const;
155 MCRegister PhysReg) const;
160 MCRegister PhysReg) const;
176 bool isRegUsedAfter(MachineInstr *MI, MCRegister PhysReg) const;
183 int getClearance(MachineInstr *MI, MCRegister PhysReg) const;
187 void getReachingLocalUses(MachineInstr *MI, MCRegister PhysReg,
194 void getLiveOuts(MachineBasicBlock *MBB, MCRegister PhysReg,
200 bool getLiveInUses(MachineBasicBlock *MBB, MCRegister PhysReg,
239 bool isSafeToDefRegAt(MachineInstr *MI, MCRegister PhysReg,
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H A DLiveRegMatrix.h108 MCRegister PhysReg);
115 bool checkInterference(SlotIndex Start, SlotIndex End, MCRegister PhysReg);
120 void assign(const LiveInterval &VirtReg, MCRegister PhysReg);
128 bool isPhysRegUsed(MCRegister PhysReg) const;
141 MCRegister PhysReg = MCRegister::NoRegister);
147 MCRegister PhysReg);
159 Register getOneVReg(unsigned PhysReg) const;
H A DRegisterClassInfo.h119 MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const { in getLastCalleeSavedAlias() argument
120 if (PhysReg.id() < CalleeSavedAliases.size()) in getLastCalleeSavedAlias()
121 return CalleeSavedAliases[PhysReg]; in getLastCalleeSavedAlias()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DRegisterAliasing.cpp17 for (const size_t PhysReg : SourceBits.set_bits()) { in getAliasedBits() local
19 for (auto Itr = RegAliasItr(PhysReg, &RegInfo, true); Itr.isValid(); in getAliasedBits()
35 for (MCPhysReg PhysReg : RegClass) in RegisterAliasingTracker() local
36 if (!ReservedReg[PhysReg]) // Removing reserved registers. in RegisterAliasingTracker()
37 SourceBits.set(PhysReg); in RegisterAliasingTracker()
44 SourceBits.set(PhysReg); in RegisterAliasingTracker()
51 for (const size_t PhysReg : SourceBits.set_bits()) { in FillOriginAndAliasedBits() local
55 Origins[*Itr] = PhysReg; in FillOriginAndAliasedBits()
66 RegisterAliasingTrackerCache::getRegister(MCPhysReg PhysReg) const { in getRegister()
67 auto &Found = Registers[PhysReg]; in getRegister()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIPreAllocateWWMRegs.cpp103 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef() local
104 if (!MRI->isPhysRegUsed(PhysReg) && in processDef()
105 Matrix->checkInterference(LI, PhysReg) == LiveRegMatrix::IK_Free) { in processDef()
106 Matrix->assign(LI, PhysReg); in processDef()
107 assert(PhysReg != 0); in processDef()
130 Register PhysReg = VRM->getPhys(VirtReg); in rewriteRegs() local
133 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewriteRegs()
137 MO.setReg(PhysReg); in rewriteRegs()
148 const Register PhysReg = VRM->getPhys(Reg); in rewriteRegs() local
149 assert(PhysReg != 0); in rewriteRegs()
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp83 Register PhysReg, in assignValueToReg() argument
85 markPhysRegUsed(PhysReg); in assignValueToReg()
86 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
121 void FormalArgHandler::markPhysRegUsed(unsigned PhysReg) { in markPhysRegUsed() argument
122 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
123 MIRBuilder.getMBB().addLiveIn(PhysReg); in markPhysRegUsed()
H A DPPCCallLowering.h48 void assignValueToReg(Register ValVReg, Register PhysReg,
58 virtual void markPhysRegUsed(unsigned PhysReg) = 0;
63 void markPhysRegUsed(unsigned PhysReg) override;
/llvm-project-15.0.7/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp38 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
40 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
42 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
128 Register PhysReg, in assignValueToReg() argument
130 MIRBuilder.getMRI()->addLiveIn(PhysReg); in assignValueToReg()
131 MIRBuilder.getMBB().addLiveIn(PhysReg); in assignValueToReg()
132 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
163 void CallReturnHandler::assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg() argument
165 MIB.addDef(PhysReg, RegState::Implicit); in assignValueToReg()
166 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp112 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
121 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
122 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
294 markPhysRegUsed(PhysReg); in assignValueToReg()
296 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
348 virtual void markPhysRegUsed(unsigned PhysReg) = 0;
355 void markPhysRegUsed(unsigned PhysReg) override { in markPhysRegUsed()
356 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
357 MIRBuilder.getMBB().addLiveIn(PhysReg); in markPhysRegUsed()
428 void markPhysRegUsed(unsigned PhysReg) override { in markPhysRegUsed()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallLowering.cpp107 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
109 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
111 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
197 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
199 markPhysRegUsed(PhysReg); in assignValueToReg()
206 virtual void markPhysRegUsed(unsigned PhysReg) = 0;
216 void markPhysRegUsed(unsigned PhysReg) override { in markPhysRegUsed()
217 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
218 MIRBuilder.getMBB().addLiveIn(PhysReg); in markPhysRegUsed()
227 void markPhysRegUsed(unsigned PhysReg) override { in markPhysRegUsed()
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/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp42 Register PhysReg = VRM->getPhys(MO.getReg()); in getRC32() local
43 if (SystemZ::GR32BitRegClass.contains(PhysReg)) in getRC32()
45 assert (SystemZ::GRH32BitRegClass.contains(PhysReg) && in getRC32()
110 Register PhysReg = Register::isPhysicalRegister(Reg) in getRegAllocationHints() local
113 if (PhysReg) { in getRegAllocationHints()
115 PhysReg = getSubReg(PhysReg, MO->getSubReg()); in getRegAllocationHints()
117 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(), in getRegAllocationHints()
119 if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg)) in getRegAllocationHints()
120 TwoAddrHints.insert(PhysReg); in getRegAllocationHints()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp95 void assignValueToReg(Register ValVReg, Register PhysReg,
108 virtual void markPhysRegUsed(unsigned PhysReg) { in markPhysRegUsed() argument
109 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
110 MIRBuilder.getMBB().addLiveIn(PhysReg); in markPhysRegUsed()
121 void markPhysRegUsed(unsigned PhysReg) override { in markPhysRegUsed() argument
122 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
133 markPhysRegUsed(PhysReg); in assignValueToReg()
134 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
202 void assignValueToReg(Register ValVReg, Register PhysReg,
223 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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