Lines Matching refs:PhysReg
97 MCPhysReg PhysReg = 0; ///< Currently held here. member
159 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
160 bool isPhysRegFree(MCPhysReg PhysReg) const;
163 void markRegUsedInInstr(MCPhysReg PhysReg) { in markRegUsedInInstr() argument
164 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in markRegUsedInInstr()
169 bool isClobberedByRegMasks(MCPhysReg PhysReg) const { in isClobberedByRegMasks()
170 return llvm::any_of(RegMasks, [PhysReg](const uint32_t *Mask) { in isClobberedByRegMasks()
171 return MachineOperand::clobbersPhysReg(Mask, PhysReg); in isClobberedByRegMasks()
176 bool isRegUsedInInstr(MCPhysReg PhysReg, bool LookAtPhysRegUses) const { in isRegUsedInInstr() argument
177 if (LookAtPhysRegUses && isClobberedByRegMasks(PhysReg)) in isRegUsedInInstr()
179 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in isRegUsedInInstr()
190 void markPhysRegUsedInInstr(MCPhysReg PhysReg) { in markPhysRegUsedInInstr() argument
191 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in markPhysRegUsedInInstr()
196 void unmarkRegUsedInInstr(MCPhysReg PhysReg) { in unmarkRegUsedInInstr() argument
197 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in unmarkRegUsedInInstr()
247 bool usePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
248 bool definePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
249 bool displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
250 void freePhysReg(MCPhysReg PhysReg);
252 unsigned calcSpillCost(MCPhysReg PhysReg) const;
262 void assignVirtToPhysReg(MachineInstr &MI, LiveReg &, MCPhysReg PhysReg);
279 void setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
288 MCPhysReg PhysReg);
303 void RegAllocFast::setPhysRegState(MCPhysReg PhysReg, unsigned NewState) { in setPhysRegState() argument
304 for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) in setPhysRegState()
308 bool RegAllocFast::isPhysRegFree(MCPhysReg PhysReg) const { in isPhysRegFree()
309 for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) { in isPhysRegFree()
483 MCPhysReg PhysReg) { in reload() argument
485 << printReg(PhysReg, TRI) << '\n'); in reload()
488 TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI); in reload()
529 MCPhysReg Reg = P.PhysReg; in reloadAtBegin()
543 MCPhysReg PhysReg = LR.PhysReg; in reloadAtBegin() local
544 if (PhysReg == 0) in reloadAtBegin()
547 MCRegister FirstUnit = *MCRegUnitIterator(PhysReg, TRI); in reloadAtBegin()
554 if (PrologLiveIns.count(PhysReg)) { in reloadAtBegin()
558 reload(MBB.begin(), LR.VirtReg, PhysReg); in reloadAtBegin()
560 reload(InsertBefore, LR.VirtReg, PhysReg); in reloadAtBegin()
585 bool RegAllocFast::displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg) { in displacePhysReg() argument
588 for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) { in displacePhysReg()
596 reload(ReloadBefore, VirtReg, LRI->PhysReg); in displacePhysReg()
598 setPhysRegState(LRI->PhysReg, regFree); in displacePhysReg()
599 LRI->PhysReg = 0; in displacePhysReg()
615 void RegAllocFast::freePhysReg(MCPhysReg PhysReg) { in freePhysReg() argument
616 LLVM_DEBUG(dbgs() << "Freeing " << printReg(PhysReg, TRI) << ':'); in freePhysReg()
618 MCRegister FirstUnit = *MCRegUnitIterator(PhysReg, TRI); in freePhysReg()
625 setPhysRegState(PhysReg, regFree); in freePhysReg()
631 setPhysRegState(LRI->PhysReg, regFree); in freePhysReg()
632 LRI->PhysReg = 0; in freePhysReg()
642 unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { in calcSpillCost()
643 for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) { in calcSpillCost()
649 << printReg(PhysReg, TRI) << '\n'); in calcSpillCost()
698 MCPhysReg PhysReg) { in assignVirtToPhysReg() argument
701 << printReg(PhysReg, TRI) << '\n'); in assignVirtToPhysReg()
702 assert(LR.PhysReg == 0 && "Already assigned a physreg"); in assignVirtToPhysReg()
703 assert(PhysReg != 0 && "Trying to assign no register"); in assignVirtToPhysReg()
704 LR.PhysReg = PhysReg; in assignVirtToPhysReg()
705 setPhysRegState(PhysReg, VirtReg); in assignVirtToPhysReg()
707 assignDanglingDebugValues(AtMI, VirtReg, PhysReg); in assignVirtToPhysReg()
754 assert(LR.PhysReg == 0); in allocVirtReg()
800 for (MCPhysReg PhysReg : AllocationOrder) { in allocVirtReg() local
801 LLVM_DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << ' '); in allocVirtReg()
802 if (isRegUsedInInstr(PhysReg, LookAtPhysRegUses)) { in allocVirtReg()
807 unsigned Cost = calcSpillCost(PhysReg); in allocVirtReg()
811 assignVirtToPhysReg(MI, LR, PhysReg); in allocVirtReg()
815 if (PhysReg == Hint0 || PhysReg == Hint1) in allocVirtReg()
819 BestReg = PhysReg; in allocVirtReg()
833 LR.PhysReg = 0; in allocVirtReg()
847 MCPhysReg PhysReg; in allocVirtRegUndef() local
848 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) { in allocVirtRegUndef()
849 PhysReg = LRI->PhysReg; in allocVirtRegUndef()
854 PhysReg = AllocationOrder[0]; in allocVirtRegUndef()
859 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
862 MO.setReg(PhysReg); in allocVirtRegUndef()
872 MCPhysReg PrevReg = LRI->PhysReg; in defineLiveThroughVirtReg()
877 LRI->PhysReg = 0; in defineLiveThroughVirtReg()
881 LLVM_DEBUG(dbgs() << "Copy " << printReg(LRI->PhysReg, TRI) << " to " in defineLiveThroughVirtReg()
885 .addReg(LRI->PhysReg, llvm::RegState::Kill); in defineLiveThroughVirtReg()
917 if (LRI->PhysReg == 0) in defineVirtReg()
920 assert(!isRegUsedInInstr(LRI->PhysReg, LookAtPhysRegUses) && in defineVirtReg()
924 << printReg(LRI->PhysReg, TRI) << '\n'); in defineVirtReg()
927 MCPhysReg PhysReg = LRI->PhysReg; in defineVirtReg() local
928 assert(PhysReg != 0 && "Register not assigned"); in defineVirtReg()
936 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut); in defineVirtReg()
943 BundleVirtRegsMap[VirtReg] = PhysReg; in defineVirtReg()
945 markRegUsedInInstr(PhysReg); in defineVirtReg()
946 setPhysReg(MI, MO, PhysReg); in defineVirtReg()
972 if (LRI->PhysReg == 0) { in useVirtReg()
992 BundleVirtRegsMap[VirtReg] = LRI->PhysReg; in useVirtReg()
994 markRegUsedInInstr(LRI->PhysReg); in useVirtReg()
995 setPhysReg(MI, MO, LRI->PhysReg); in useVirtReg()
1002 MCPhysReg PhysReg) { in setPhysReg() argument
1004 MO.setReg(PhysReg); in setPhysReg()
1010 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : MCRegister()); in setPhysReg()
1021 MI.addRegisterKilled(PhysReg, TRI, true); in setPhysReg()
1029 MI.addRegisterDead(PhysReg, TRI, true); in setPhysReg()
1031 MI.addRegisterDefined(PhysReg, TRI); in setPhysReg()
1058 assert(TRI->hasRegUnit(I->PhysReg, Unit) && "inverse mapping present"); in dumpState()
1068 MCPhysReg PhysReg = LR.PhysReg; in dumpState() local
1069 if (PhysReg != 0) { in dumpState()
1070 assert(Register::isPhysicalRegister(PhysReg) && in dumpState()
1072 for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) { in dumpState()
1315 MCPhysReg PhysReg = LR.PhysReg; in allocateInstruction() local
1316 if (PhysReg != 0 && isClobberedByRegMasks(PhysReg)) in allocateInstruction()
1317 displacePhysReg(MI, PhysReg); in allocateInstruction()
1440 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) { in handleDebugValue()
1443 setPhysReg(MI, *RegMO, LRI->PhysReg); in handleDebugValue()
1485 setPhysRegState(LiveReg.PhysReg, regPreAssigned); in allocateBasicBlock()