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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init |
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8d0383eb |
| 24-Jun-2022 |
Matt Arsenault <[email protected]> |
CodeGen: Remove AliasAnalysis from regalloc
This was stored in LiveIntervals, but not actually used for anything related to LiveIntervals. It was only used in one check for if a load instruction is
CodeGen: Remove AliasAnalysis from regalloc
This was stored in LiveIntervals, but not actually used for anything related to LiveIntervals. It was only used in one check for if a load instruction is rematerializable. I also don't think this was entirely correct, since it was implicitly assuming constant loads are also dereferenceable.
Remove this and rely only on the invariant+dereferenceable flags in the memory operand. Set the flag based on the AA query upfront. This should have the same net benefit, but has the possible disadvantage of making this AA query nonlazy.
Preserve the behavior of assuming pointsToConstantMemory implying dereferenceable for now, but maybe this should be changed.
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Revision tags: llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3 |
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c35ad9ee |
| 27-Apr-2022 |
Mircea Trofin <[email protected]> |
[mlgo] Support exposing more features than those supported by models
This allows the compiler to support more features than those supported by a model. The only requirement (development mode only) i
[mlgo] Support exposing more features than those supported by models
This allows the compiler to support more features than those supported by a model. The only requirement (development mode only) is that the new features must be appended at the end of the list of features requested from the model. The support is transparent to compiler code: for unsupported features, we provide a valid buffer to copy their values; it's just that this buffer is disconnected from the model, so insofar as the model is concerned (AOT or development mode), these features don't exist. The buffers are allocated at setup - meaning, at steady state, there is no extra allocation (maintaining the current invariant). These buffers has 2 roles: one, keep the compiler code simple. Second, allow logging their values in development mode. The latter allows retraining a model supporting the larger feature set starting from traces produced with the old model.
For release mode (AOT-ed models), this decouples compiler evolution from model evolution, which we want in scenarios where the toolchain is frequently rebuilt and redeployed: we can first deploy the new features, and continue working with the older model, until a new model is made available, which can then be picked up the next time the compiler is built.
Differential Revision: https://reviews.llvm.org/D124565
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Revision tags: llvmorg-14.0.2, llvmorg-14.0.1 |
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f658ca1a |
| 21-Mar-2022 |
Mircea Trofin <[email protected]> |
[mlgo] Fix build breaks introduced by includes cleanups
These were not detected by the build bots because those went quietly offline, too, due to a misconfiguration (fixed since)
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989f1c72 |
| 15-Mar-2022 |
serge-sans-paille <[email protected]> |
Cleanup codegen includes
This is a (fixed) recommit of https://reviews.llvm.org/D121169
after: 1061034926 before: 1063332844
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-in
Cleanup codegen includes
This is a (fixed) recommit of https://reviews.llvm.org/D121169
after: 1061034926 before: 1063332844
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D121681
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Revision tags: llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3 |
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a278250b |
| 10-Mar-2022 |
Nico Weber <[email protected]> |
Revert "Cleanup codegen includes"
This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20. Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang, and many LLVM tests, see comments on https:/
Revert "Cleanup codegen includes"
This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20. Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang, and many LLVM tests, see comments on https://reviews.llvm.org/D121169
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7f230fee |
| 07-Mar-2022 |
serge-sans-paille <[email protected]> |
Cleanup codegen includes
after: 1061034926 before: 1063332844
Differential Revision: https://reviews.llvm.org/D121169
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Revision tags: llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1 |
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5a50ab4d |
| 08-Feb-2022 |
Mircea Trofin <[email protected]> |
[nfc][mlgo][regalloc] Stop warnings about unused function
Added a `NoopSavedModelImpl` type which can be used as a mock AOT-ed saved model, and further minimize conditional compilation cases. This a
[nfc][mlgo][regalloc] Stop warnings about unused function
Added a `NoopSavedModelImpl` type which can be used as a mock AOT-ed saved model, and further minimize conditional compilation cases. This also removes unused function warnings on gcc.
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Revision tags: llvmorg-15-init |
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91a33ad3 |
| 01-Feb-2022 |
Mircea Trofin <[email protected]> |
[nfc][mlgo][regalloc] Cache live interval feature components
Lazily cache the feature components of a LiveInterval.
Differential Revision: https://reviews.llvm.org/D118674
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592f52de |
| 03-Feb-2022 |
Mircea Trofin <[email protected]> |
[nfc][regalloc] const LiveIntervals within the allocator
Once built, LiveIntervals are immutable. This patch captures that.
Differential Revision: https://reviews.llvm.org/D118918
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79b98f0a |
| 03-Feb-2022 |
Mircea Trofin <[email protected]> |
Revert "[nfc][mlgo] De-const a parameter"
This reverts commit bc3b372161716a4c4845d47a877e4892df0d08da.
The planned change that would have needed non-const MachineFunction refs isn't needed after a
Revert "[nfc][mlgo] De-const a parameter"
This reverts commit bc3b372161716a4c4845d47a877e4892df0d08da.
The planned change that would have needed non-const MachineFunction refs isn't needed after all.
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660ff655 |
| 02-Feb-2022 |
Mircea Trofin <[email protected]> |
Fix buildbreak introduced in ed2deab5956fea9e8f64ef6020fe0b4e19734ecc
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ed2deab5 |
| 01-Feb-2022 |
Mircea Trofin <[email protected]> |
[nfc][regalloc] Make the max inference cutoff configurable
Added a flag to make configurable the number of interferences after which we 'bail out' and treat a set of intervals as un-evictable. Also
[nfc][regalloc] Make the max inference cutoff configurable
Added a flag to make configurable the number of interferences after which we 'bail out' and treat a set of intervals as un-evictable. Also using it on the ML side, as it turns out to be a good control for compile-time.
With this configurable, we can do a bit of trial and error and see if bumping it has any effect on heuristic/policy quality.
Differential Revision: https://reviews.llvm.org/D118707
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a3f14918 |
| 01-Feb-2022 |
Mircea Trofin <[email protected]> |
[nfc][mlgo][regalloc] 'hasPreferredPhys' out of feature components
It isn't cacheable, it can be updated by other events than live interval resizing.
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9aa2c914 |
| 31-Jan-2022 |
Mircea Trofin <[email protected]> |
[mlgo][regalloc] Factor live interval feature calculation
Factoring it out so we can subsequently cache it. This should be a NFC, however, for the float quantities, we see small errors in the least
[mlgo][regalloc] Factor live interval feature calculation
Factoring it out so we can subsequently cache it. This should be a NFC, however, for the float quantities, we see small errors in the least significant digits. This is because, before, we were summing up one by one. Now, we sum up results of sums.
This shouldn't matter for ML, and will require rework when we do quantization (avoiding floats altogether), but meanwhile, it did require an update to the reference file used for testing.
The patch also bumps the precision of the variables involved in this, to reduce the error (note they are casted back to float at the end by the SET macro, since we only work with float and not double in TF)
Differential Revision: https://reviews.llvm.org/D118659
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bc3b3721 |
| 31-Jan-2022 |
Mircea Trofin <[email protected]> |
[nfc][mlgo] De-const a parameter
We plan to pass the MachineFunction& to APIs that expect it non-const (for legitimate reasons). The advisor still holds the ref as a const ref, though, so we keep mo
[nfc][mlgo] De-const a parameter
We plan to pass the MachineFunction& to APIs that expect it non-const (for legitimate reasons). The advisor still holds the ref as a const ref, though, so we keep most of the maintainability value of that.
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0e691aed |
| 30-Jan-2022 |
Fangrui Song <[email protected]> |
[mlgo][regalloc] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after a8a7bf922cea8af01168f7a4adf4ed0365bcc2b4
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a8a7bf92 |
| 30-Jan-2022 |
Mircea Trofin <[email protected]> |
[mlgo][regalloc] Fix register masking
If AllocationOrder has less than 32 elements, we were treating the extra positions as if they were valid. This was detected by a subsequent assert. The fix also
[mlgo][regalloc] Fix register masking
If AllocationOrder has less than 32 elements, we were treating the extra positions as if they were valid. This was detected by a subsequent assert. The fix also tightens the asserts.
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b1af01fe |
| 24-Jan-2022 |
Mircea Trofin <[email protected]> |
[NFC][MLGO] Simplify conditional compilation
Most of the code that's shared between 'release' and 'development' modes doesn't depend on anything special.
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Revision tags: llvmorg-13.0.1, llvmorg-13.0.1-rc3 |
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f29256a6 |
| 20-Jan-2022 |
Mircea Trofin <[email protected]> |
[MLGO] Improved support for AOT cross-targeting scenarios
The tensorflow AOT compiler can cross-target, but it can't run on (for example) arm64. We added earlier support where the AOT-ed header and
[MLGO] Improved support for AOT cross-targeting scenarios
The tensorflow AOT compiler can cross-target, but it can't run on (for example) arm64. We added earlier support where the AOT-ed header and object would be built on a separate builder and then passed at build time to a build host where the AOT compiler can't run, but clang can be otherwise built.
To simplify such scenarios given we now support more than one AOT-able case (regalloc and inliner), we make the AOT scenario centered on whether files are generated, case by case (this includes the "passed from a different builder" scenario). This means we shouldn't need an 'umbrella' LLVM_HAVE_TF_AOT, in favor of case by case control. A builder can opt out of an AOT case by passing that case's model path as `none`. Note that the overrides still take precedence.
This patch controls conditional compilation with case-specific flags, which can be enabled locally, for the component where those are available. We still keep an overall flag for some tests.
The 'development/training' mode is unchanged, because there the model is passed from the command line and interpreted.
Differential Revision: https://reviews.llvm.org/D117752
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073e0968 |
| 19-Jan-2022 |
Mircea Trofin <[email protected]> |
Fix build break introduced by D117147
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Revision tags: llvmorg-13.0.1-rc2 |
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e67430cc |
| 22-Dec-2021 |
Mircea Trofin <[email protected]> |
[MLGO] ML Regalloc Eviction Advisor
The bulk of the implementation is common between 'release' mode (==AOT-ed model) and 'development' mode (for training), the main difference is that in development
[MLGO] ML Regalloc Eviction Advisor
The bulk of the implementation is common between 'release' mode (==AOT-ed model) and 'development' mode (for training), the main difference is that in development mode, we may also log features (for training logs), inject scoring information (currently after the Virtual Register Rewriter) and then produce the log file.
This patch also introduces the score injection pass, 'Register Allocation Pass Scoring', which is trivially just logging the score in development mode.
Differential Revision: https://reviews.llvm.org/D117147
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b2d2e931 |
| 12-Jan-2022 |
Mircea Trofin <[email protected]> |
[NFC][MLGO] The regalloc reward is float, not int64_t
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3150bce0 |
| 12-Jan-2022 |
Mircea Trofin <[email protected]> |
[NFC][MLGO] Prep a few files before the main ML Regalloc adviser
To avoid trivial changes.
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410480e3 |
| 07-Jan-2022 |
Kazu Hirata <[email protected]> |
Ensure newlines at the end of files (NFC)
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68ac7b17 |
| 21-Dec-2021 |
Mircea Trofin <[email protected]> |
[NFC][mlgo] Add feature declarations for the ML regalloc advisor
This just adds feature declarations and some boilerplate.
Differential Revision: https://reviews.llvm.org/D116076
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