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Searched refs:OrigMI (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNDPPCombine.cpp199 auto OrigOp = OrigMI.getOpcode(); in createDPPInst()
219 auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI, in createDPPInst()
221 .setMIFlags(OrigMI.getFlags()); in createDPPInst()
599 auto &OrigMI = *Use->getParent(); in combineDPPMov() local
600 LLVM_DEBUG(dbgs() << " try: " << OrigMI); in combineDPPMov()
602 auto OrigOp = OrigMI.getOpcode(); in combineDPPMov()
632 bool IsShrinkable = isShrinkable(OrigMI); in combineDPPMov()
661 << " " << OrigMI in combineDPPMov()
675 auto *BB = OrigMI.getParent(); in combineDPPMov()
677 BB->insert(OrigMI, NewMI); in combineDPPMov()
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp105 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI, in allUsesAvailableAt() argument
110 for (const MachineOperand &MO : OrigMI->operands()) { in allUsesAvailableAt()
165 assert(RM.OrigMI && "No defining instruction for remattable value"); in canRematerializeAt()
166 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); in canRematerializeAt()
169 if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI)) in canRematerializeAt()
173 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
185 assert(RM.OrigMI && "Invalid remat"); in rematerializeAt()
186 TII.reMaterialize(MBB, MI, DestReg, 0, *RM.OrigMI, tri); in rematerializeAt()
H A DInlineSpiller.cpp592 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def); in reMaterializeFor()
610 if (RM.OrigMI->canFoldAsLoad() && in reMaterializeFor()
611 foldMemoryOperand(Ops, RM.OrigMI)) { in reMaterializeFor()
H A DModuloSchedule.cpp1142 MachineInstr *OrigMI = OrigInstr->second; in rewriteScheduledInstr() local
1143 int StageSched = Schedule.getStage(OrigMI); in rewriteScheduledInstr()
1144 int CycleSched = Schedule.getCycle(OrigMI); in rewriteScheduledInstr()
1152 (CyclePhi <= CycleSched || OrigMI->isPHI())) in rewriteScheduledInstr()
H A DRegisterCoalescer.cpp206 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
612 bool RegisterCoalescer::allUsesAvailableAt(const MachineInstr *OrigMI, in allUsesAvailableAt() argument
617 .allUsesAvailableAt(OrigMI, OrigIdx, UseIdx); in allUsesAvailableAt()
H A DSplitKit.cpp601 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def); in defFromParent()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FixupBWInsts.cpp85 bool getSuperRegDestIfDead(MachineInstr *OrigMI,
191 bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI, in getSuperRegDestIfDead() argument
194 Register OrigDestReg = OrigMI->getOperand(0).getReg(); in getSuperRegDestIfDead()
253 unsigned Opc = OrigMI->getOpcode(); (void)Opc; in getSuperRegDestIfDead()
262 for (auto &MO: OrigMI->implicit_operands()) { in getSuperRegDestIfDead()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSExtWRemoval.cpp75 static bool isAllUsesReadW(const MachineInstr &OrigMI, in isAllUsesReadW() argument
81 Visited.insert(&OrigMI); in isAllUsesReadW()
82 addUses(OrigMI, Worklist, MRI); in isAllUsesReadW()
90 if (MI == &OrigMI) { in isAllUsesReadW()
293 static bool isSignExtendedW(MachineInstr &OrigMI, MachineRegisterInfo &MRI, in isSignExtendedW() argument
299 Worklist.push_back(&OrigMI); in isSignExtendedW()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DLiveRangeEdit.h194 MachineInstr *OrigMI = nullptr; // Instruction defining OrigVNI. It contains member
202 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,