63   MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI,
68   MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI,
189 MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,  in createDPPInst()  argument
199   auto OrigOp = OrigMI.getOpcode();  in createDPPInst()
219   auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI,  in createDPPInst()
220                          OrigMI.getDebugLoc(), TII->get(DPPOp))  in createDPPInst()
221     .setMIFlags(OrigMI.getFlags());  in createDPPInst()
226     if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) {  in createDPPInst()
230     if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) {  in createDPPInst()
262     if (auto *Mod0 = TII->getNamedOperand(OrigMI,  in createDPPInst()
286     if (auto *Mod1 = TII->getNamedOperand(OrigMI,  in createDPPInst()
299     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);  in createDPPInst()
310             TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2_modifiers)) {  in createDPPInst()
318     auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2);  in createDPPInst()
330       auto *ClampOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::clamp);  in createDPPInst()
335       auto *VdstInOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst_in);  in createDPPInst()
340       auto *OmodOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::omod);  in createDPPInst()
348               TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel)) {  in createDPPInst()
359               TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel_hi)) {  in createDPPInst()
372       auto *NegOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_lo);  in createDPPInst()
377       auto *NegHiOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_hi);  in createDPPInst()
450     MachineInstr &OrigMI, MachineInstr &MovMI, RegSubRegPair CombOldVGPR,  in createDPPInst()  argument
454     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);  in createDPPInst()
459     if (!isIdentityValue(OrigMI.getOpcode(), OldOpndValue)) {  in createDPPInst()
471   return createDPPInst(OrigMI, MovMI, CombOldVGPR, CombBCZ, IsShrinkable);  in createDPPInst()
599     auto &OrigMI = *Use->getParent();  in combineDPPMov()  local
600     LLVM_DEBUG(dbgs() << "  try: " << OrigMI);  in combineDPPMov()
602     auto OrigOp = OrigMI.getOpcode();  in combineDPPMov()
604       Register FwdReg = OrigMI.getOperand(0).getReg();  in combineDPPMov()
607       if (execMayBeModifiedBeforeAnyUse(*MRI, FwdReg, OrigMI)) {  in combineDPPMov()
613       unsigned OpNo, E = OrigMI.getNumOperands();  in combineDPPMov()
615         if (OrigMI.getOperand(OpNo).getReg() == DPPMovReg) {  in combineDPPMov()
616           FwdSubReg = OrigMI.getOperand(OpNo + 1).getImm();  in combineDPPMov()
628       RegSeqWithOpNos[&OrigMI].push_back(OpNo);  in combineDPPMov()
632     bool IsShrinkable = isShrinkable(OrigMI);  in combineDPPMov()
641     if (OrigMI.modifiesRegister(AMDGPU::EXEC, ST->getRegisterInfo())) {  in combineDPPMov()
646     auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0);  in combineDPPMov()
647     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);  in combineDPPMov()
648     if (Use != Src0 && !(Use == Src1 && OrigMI.isCommutable())) { // [1]  in combineDPPMov()
653     auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2);  in combineDPPMov()
661           << "  " << OrigMI  in combineDPPMov()
666     LLVM_DEBUG(dbgs() << "  combining: " << OrigMI);  in combineDPPMov()
668       if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR,  in combineDPPMov()
674       assert(Use == Src1 && OrigMI.isCommutable()); // by check [1]  in combineDPPMov()
675       auto *BB = OrigMI.getParent();  in combineDPPMov()
676       auto *NewMI = BB->getParent()->CloneMachineInstr(&OrigMI);  in combineDPPMov()
677       BB->insert(OrigMI, NewMI);  in combineDPPMov()
692     OrigMIs.push_back(&OrigMI);  in combineDPPMov()