Home
last modified time | relevance | path

Searched refs:OPT (Results 1 – 25 of 155) sorted by relevance

1234567

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dlower-mem-intrinsics.ll58 ; OPT: memcpy-split:
65 ; OPT-NEXT: ret void
137 ; OPT-NEXT: ret void
174 ; OPT: split:
175 ; OPT-NEXT: ret void
212 ; OPT-NEXT: ret void
252 ; OPT-NEXT: ret void
321 ; OPT-NEXT: ret void
365 ; OPT-NEXT: ret void
498 ; OPT-NEXT: ret void
[all …]
H A Dcgp-bitfield-extract.ll10 ; OPT: entry:
13 ; OPT: bb0:
18 ; OPT: bb1:
23 ; OPT: ret:
24 ; OPT: store
25 ; OPT: ret
63 ; OPT: bb0:
68 ; OPT: bb1:
73 ; OPT: ret:
75 ; OPT: ret
[all …]
H A Dpropagate-attributes-clone.ll1 ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -O1 < %s | FileCheck -check-prefixes=OPT,OPT-EXT %s
2 …-S -mtriple=amdgcn-amd-amdhsa -passes='default<O1>' < %s | FileCheck -check-prefixes=OPT,OPT-EXT %s
15 ; OPT-EXT: tail call void @foo4()
16 ; OPT-EXT: tail call void @foo3()
17 ; OPT-EXT: tail call void @foo2()
18 ; OPT-EXT: tail call void @foo2()
28 ; OPT: ret void
32 ; OPT: ret void
36 ; OPT: ret void
40 ; OPT: ret void
[all …]
H A Dwiden_extending_scalar_loads.ll6 ; OPT: load i1
7 ; OPT-NEXT: store i1
15 ; OPT: load i1
16 ; OPT-NEXT: store
24 ; OPT: bitcast
26 ; OPT-NEXT: trunc
35 ; OPT: load i8
44 ; OPT: load i8
53 ; OPT: bitcast
74 ; OPT: bitcast
[all …]
H A Dmultilevel-break.ll10 ; OPT-NEXT: main_body:
12 ; OPT: LOOP.outer:
16 ; OPT: LOOP:
25 ; OPT: Flow:
35 ; OPT: Flow1:
39 ; OPT: IF:
42 ; OPT: ENDIF:
116 ; OPT-NEXT: bb:
120 ; OPT: bb1:
148 ; OPT: Flow:
[all …]
H A Dllvm.amdgcn.wavefrontsize.ll7 ; RUN: opt -O3 -S < %s | FileCheck -check-prefixes=OPT,OPT-WXX %s
8 ; RUN: opt -mtriple=amdgcn-- -O3 -S < %s | FileCheck -check-prefixes=OPT,OPT-WXX %s
9 …pt -mtriple=amdgcn-- -O3 -mattr=+wavefrontsize32 -S < %s | FileCheck -check-prefixes=OPT,OPT-W32 %s
11 …pt -mtriple=amdgcn-- -O3 -mattr=+wavefrontsize64 -S < %s | FileCheck -check-prefixes=OPT,OPT-W64 %s
12 ; RUN: opt -mtriple=amdgcn-- -mcpu=tonga -O3 -S < %s | FileCheck -check-prefixes=OPT,OPT-W64 %s
29 ; OPT-NEXT: ret void
49 ; OPT-WXX: %tmp1 = icmp ugt i32 %tmp, 32
52 ; OPT-NEXT: ret void
66 ; OPT: bb:
69 ; OPT-WXX: bb3:
[all …]
H A Dloop_break.ll8 ; OPT-NEXT: bb:
12 ; OPT: bb1:
18 ; OPT: bb4:
22 ; OPT: Flow:
27 ; OPT: bb9:
85 ; OPT-NEXT: bb:
89 ; OPT: bb1:
95 ; OPT: bb4:
104 ; OPT: bb9:
176 ; OPT-NEXT: bb:
[all …]
H A Dcgp-addressing-modes-flat.ll1 …riple=amdgcn-unknown-unknown -mcpu=bonaire < %s | FileCheck --check-prefixes=OPT,OPT-CI,OPT-CIVI %s
10 ; OPT-CIVI: br i1
13 ; OPT-GFX9: br
44 ; OPT: br i1
49 ; OPT: br label
77 ; OPT: br i1
82 ; OPT: br label
109 ; OPT-CIVI: br
113 ; OPT-GFX9: br
144 ; OPT: br
[all …]
H A Dsi-annotatecfg-multiple-backedges.ll9 ; OPT-LABEL: @multiple_backedges(
10 ; OPT-NEXT: entry:
12 ; OPT-NEXT: [[TMP2:%.*]] = shl nsw i32 [[ARG:%.*]], 1
13 ; OPT-NEXT: br label [[LOOP:%.*]]
14 ; OPT: loop:
18 ; OPT-NEXT: [[TMP5]] = add nsw i32 [[TMP4]], [[TMP]]
19 ; OPT-NEXT: [[TMP6:%.*]] = icmp slt i32 [[ARG]], [[TMP5]]
23 ; OPT: loop_end:
29 ; OPT: loop_exit:
31 ; OPT-NEXT: [[TMP12:%.*]] = zext i32 [[TMP]] to i64
[all …]
H A Dunstructured-cfg-def-use-issue.ll62 ; SI-OPT-NEXT: bb:
66 ; SI-OPT: bb2:
69 ; SI-OPT: bb4:
72 ; SI-OPT: bb6:
74 ; SI-OPT: bb7:
77 ; SI-OPT: bb9:
125 ; SI-OPT-NEXT: bb:
128 ; SI-OPT: bb1:
130 ; SI-OPT: bb2:
136 ; SI-OPT: bb4:
[all …]
H A Dpromote-alloca-pointer-array.ll5 ; OPT-LABEL: @test_pointer_array(
6 ; OPT-NEXT: entry:
7 ; OPT-NEXT: [[A:%.*]] = alloca [3 x i8*], align 16, addrspace(5)
9 ; OPT-NEXT: [[CAST:%.*]] = bitcast i8* addrspace(5)* [[GEP]] to i64 addrspace(5)*
11 ; OPT-NEXT: [[TMP1:%.*]] = load <3 x i8*>, <3 x i8*> addrspace(5)* [[TMP0]], align 32
12 ; OPT-NEXT: [[TMP2:%.*]] = inttoptr i64 [[V:%.*]] to i8*
13 ; OPT-NEXT: [[TMP3:%.*]] = insertelement <3 x i8*> [[TMP1]], i8* [[TMP2]], i32 0
14 ; OPT-NEXT: store <3 x i8*> [[TMP3]], <3 x i8*> addrspace(5)* [[TMP0]], align 32
17 ; OPT-NEXT: [[TMP6:%.*]] = extractelement <3 x i8*> [[TMP5]], i32 0
18 ; OPT-NEXT: [[TMP7:%.*]] = ptrtoint i8* [[TMP6]] to i64
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dconsthoist-few-dependents.ll15 ; OPT: bb1:
17 ; OPT: bb2:
19 ; OPT: bb3:
22 ; OPT-NOT: add
63 ; OPT-2: bb1:
65 ; OPT-2: bb2:
67 ; OPT-2: bb3:
122 ; OPT-1: bb1:
126 ; OPT-1: bb2:
129 ; OPT-1: bb3:
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-bitfield-extract.ll17 ; OPT-LABEL: @foo(
41 ; OPT-LABEL: @baz(
57 ; OPT-LABEL: @bar(
75 ; OPT-LABEL: @fct1(
97 ; OPT-LABEL: @fct2(
111 ; OPT-LABEL: @fct3(
127 ; OPT-LABEL: @fct4(
128 ; OPT-NEXT: entry:
153 ; OPT-LABEL: @fct5(
154 ; OPT-NEXT: entry:
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dp9-vinsert-vextract.ll153 ; CHECK-OPT-NEXT: blr
192 ; CHECK-OPT-NEXT: blr
228 ; CHECK-OPT-NEXT: blr
264 ; CHECK-OPT-NEXT: blr
301 ; CHECK-OPT-NEXT: blr
338 ; CHECK-OPT-NEXT: blr
373 ; CHECK-OPT-NEXT: blr
410 ; CHECK-OPT-NEXT: blr
867 ; CHECK-OPT-NEXT: blr
903 ; CHECK-OPT-NEXT: blr
[all …]
H A Daix-p9-insert-extract.ll153 ; CHECK-64-OPT-NEXT: blr
169 ; CHECK-32-OPT-NEXT: blr
192 ; CHECK-64-OPT-NEXT: blr
208 ; CHECK-32-OPT-NEXT: blr
229 ; CHECK-64-OPT-NEXT: blr
245 ; CHECK-32-OPT-NEXT: blr
266 ; CHECK-64-OPT-NEXT: blr
282 ; CHECK-32-OPT-NEXT: blr
303 ; CHECK-64-OPT-NEXT: blr
319 ; CHECK-32-OPT-NEXT: blr
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/ParallelDSP/
H A Dcomplex_dot_prod.ll50 ; CHECK-OPT-LABEL: @complex_dot_prod(
51 ; CHECK-OPT-NEXT: entry:
55 ; CHECK-OPT-NEXT: [[TMP3:%.*]] = sext i16 [[TMP2]] to i32
56 ; CHECK-OPT-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 16
58 ; CHECK-OPT-NEXT: [[TMP6:%.*]] = sext i16 [[TMP5]] to i32
65 ; CHECK-OPT-NEXT: [[TMP12:%.*]] = lshr i32 [[TMP8]], 16
78 ; CHECK-OPT-NEXT: [[TMP19:%.*]] = lshr i32 [[TMP16]], 16
87 ; CHECK-OPT-NEXT: [[TMP27:%.*]] = lshr i32 [[TMP23]], 16
141 ; CHECK-OPT-NEXT: [[TMP60:%.*]] = lshr i64 [[SUB86]], 6
144 ; CHECK-OPT-NEXT: [[TMP61:%.*]] = lshr i64 [[TMP55]], 6
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dfp-sincos-01.ll7 ; CHECK-OPT-LABEL: f1:
9 ; CHECK-OPT: le %f0, 164(%r15)
18 ; CHECK-OPT-LABEL: f1_errno:
20 ; CHECK-OPT: ler %f9, %f0
22 ; CHECK-OPT: aebr %f0, %f9
30 ; CHECK-OPT-LABEL: f2:
43 ; CHECK-OPT: ldr %f9, %f0
45 ; CHECK-OPT: adbr %f0, %f9
53 ; CHECK-OPT-LABEL: f3:
55 ; CHECK-OPT: axbr
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dtailcall-extract.ll12 ; OPT-LABEL: test1
16 ; OPT-NEXT: bitcast
17 ; OPT-NEXT: ret
22 ; OPT-NEXT: bitcast
23 ; OPT-NEXT: ret
57 ; OPT-LABEL: test2
67 ; OPT-NEXT: phi
69 ; OPT-NEXT: ret
107 ; OPT-NEXT: ret
113 ; OPT-NEXT: ret
[all …]
/llvm-project-15.0.7/mlir/test/Examples/Toy/Ch5/
H A Daffine-lowering.mlir42 // OPT-LABEL: func @main()
43 // OPT-DAG: [[VAL_0:%.*]] = arith.constant 1.000000e+00 : f64
44 // OPT-DAG: [[VAL_1:%.*]] = arith.constant 2.000000e+00 : f64
45 // OPT-DAG: [[VAL_2:%.*]] = arith.constant 3.000000e+00 : f64
49 // OPT: [[VAL_6:%.*]] = memref.alloc() : memref<3x2xf64>
50 // OPT: [[VAL_7:%.*]] = memref.alloc() : memref<2x3xf64>
57 // OPT: affine.for [[VAL_8:%.*]] = 0 to 3 {
58 // OPT: affine.for [[VAL_9:%.*]] = 0 to 2 {
62 // OPT: toy.print [[VAL_6]] : memref<3x2xf64>
63 // OPT: memref.dealloc [[VAL_7]] : memref<2x3xf64>
[all …]
/llvm-project-15.0.7/mlir/test/Examples/Toy/Ch7/
H A Daffine-lowering.mlir42 // OPT-LABEL: func @main()
43 // OPT-DAG: [[VAL_0:%.*]] = arith.constant 1.000000e+00 : f64
44 // OPT-DAG: [[VAL_1:%.*]] = arith.constant 2.000000e+00 : f64
45 // OPT-DAG: [[VAL_2:%.*]] = arith.constant 3.000000e+00 : f64
49 // OPT: [[VAL_6:%.*]] = memref.alloc() : memref<3x2xf64>
50 // OPT: [[VAL_7:%.*]] = memref.alloc() : memref<2x3xf64>
57 // OPT: affine.for [[VAL_8:%.*]] = 0 to 3 {
58 // OPT: affine.for [[VAL_9:%.*]] = 0 to 2 {
62 // OPT: toy.print [[VAL_6]] : memref<3x2xf64>
63 // OPT: memref.dealloc [[VAL_7]] : memref<2x3xf64>
[all …]
/llvm-project-15.0.7/mlir/test/Examples/Toy/Ch6/
H A Daffine-lowering.mlir42 // OPT-LABEL: func @main()
43 // OPT-DAG: [[VAL_0:%.*]] = arith.constant 1.000000e+00 : f64
44 // OPT-DAG: [[VAL_1:%.*]] = arith.constant 2.000000e+00 : f64
45 // OPT-DAG: [[VAL_2:%.*]] = arith.constant 3.000000e+00 : f64
49 // OPT: [[VAL_6:%.*]] = memref.alloc() : memref<3x2xf64>
50 // OPT: [[VAL_7:%.*]] = memref.alloc() : memref<2x3xf64>
57 // OPT: affine.for [[VAL_8:%.*]] = 0 to 3 {
58 // OPT: affine.for [[VAL_9:%.*]] = 0 to 2 {
62 // OPT: toy.print [[VAL_6]] : memref<3x2xf64>
63 // OPT: memref.dealloc [[VAL_7]] : memref<2x3xf64>
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/TypeBasedAliasAnalysis/
H A Daggregates.ll19 ; OPT-LABEL: f1
20 ; OPT: store i32 5,
21 ; OPT: store i32 7,
36 ; OPT-LABEL: f2
37 ; OPT: store i32 5,
53 ; OPT-LABEL: f3
70 ; OPT-LABEL: f4
88 ; OPT-LABEL: f5
91 ; OPT: ret i32 5
104 ; OPT-LABEL: f6
[all …]
H A Dtbaa-path-new.ll23 ; OPT: store i32 1,
24 ; OPT: store i32 4,
48 ; OPT: ret i32 1
66 ; OPT: store i32 1
67 ; OPT: store i32 4
92 ; OPT: ret i32 1
114 ; OPT: ret i32 1
136 ; OPT: ret i32 1
158 ; OPT: ret i32 1
180 ; OPT: ret i32 1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SPARC/
H A Dfp16-promote.ll82 ; V8-OPT: ! %bb.0:
91 ; V8-OPT-NEXT: unimp 16
96 ; V8-OPT-NEXT: ret
97 ; V8-OPT-NEXT: restore
166 ; V8-OPT: ! %bb.0:
171 ; V8-OPT-NEXT: ret
209 ; V8-OPT: ! %bb.0:
219 ; V8-OPT-NEXT: ret
278 ; V8-OPT-NEXT: ret
343 ; V8-OPT-NEXT: ret
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AArch64/
H A Dsve-intrinsic-opts-lasta-lastb.ll12 ; OPT-NEXT: ret i8 [[E0]]
24 ; OPT-NEXT: ret i8 [[E1]]
34 ; OPT-NEXT: ret i8 [[E0]]
44 ; OPT-NEXT: ret i8 [[E1]]
54 ; OPT-NEXT: ret i8 [[E2]]
64 ; OPT-NEXT: ret i8 [[E3]]
74 ; OPT-NEXT: ret i8 [[E4]]
84 ; OPT-NEXT: ret i8 [[E5]]
140 ; OPT-NEXT: ret i8 [[E]]
149 ; OPT-LABEL: @lasta_splat(
[all …]

1234567