Lines Matching refs:OPT
3 …S -mtriple=amdgcn-- -structurizecfg -si-annotate-control-flow < %s | FileCheck -check-prefix=OPT %s
9 ; OPT-LABEL: @multi_else_break(
10 ; OPT-NEXT: main_body:
11 ; OPT-NEXT: br label [[LOOP_OUTER:%.*]]
12 ; OPT: LOOP.outer:
13 ; OPT-NEXT: [[PHI_BROKEN2:%.*]] = phi i64 [ [[TMP10:%.*]], [[FLOW1:%.*]] ], [ 0, [[MAIN_BODY:%.*…
14 ; OPT-NEXT: [[TMP43:%.*]] = phi i32 [ 0, [[MAIN_BODY]] ], [ [[TMP4:%.*]], [[FLOW1]] ]
15 ; OPT-NEXT: br label [[LOOP:%.*]]
16 ; OPT: LOOP:
17 ; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP8:%.*]], [[FLOW:%.*]] ], [ 0, [[LOOP_OUTER]] ]
18 ; OPT-NEXT: [[TMP0:%.*]] = phi i32 [ undef, [[LOOP_OUTER]] ], [ [[TMP4]], [[FLOW]] ]
19 ; OPT-NEXT: [[TMP45:%.*]] = phi i32 [ [[TMP43]], [[LOOP_OUTER]] ], [ [[TMP5:%.*]], [[FLOW]] ]
20 ; OPT-NEXT: [[TMP48:%.*]] = icmp slt i32 [[TMP45]], [[UB:%.*]]
21 ; OPT-NEXT: [[TMP1:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP48]])
22 ; OPT-NEXT: [[TMP2:%.*]] = extractvalue { i1, i64 } [[TMP1]], 0
23 ; OPT-NEXT: [[TMP3:%.*]] = extractvalue { i1, i64 } [[TMP1]], 1
24 ; OPT-NEXT: br i1 [[TMP2]], label [[ENDIF:%.*]], label [[FLOW]]
25 ; OPT: Flow:
26 ; OPT-NEXT: [[TMP4]] = phi i32 [ [[TMP47:%.*]], [[ENDIF]] ], [ [[TMP0]], [[LOOP]] ]
27 ; OPT-NEXT: [[TMP5]] = phi i32 [ [[TMP47]], [[ENDIF]] ], [ undef, [[LOOP]] ]
28 ; OPT-NEXT: [[TMP6:%.*]] = phi i1 [ [[TMP51:%.*]], [[ENDIF]] ], [ true, [[LOOP]] ]
29 ; OPT-NEXT: [[TMP7:%.*]] = phi i1 [ [[TMP51_INV:%.*]], [[ENDIF]] ], [ true, [[LOOP]] ]
30 ; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP3]])
31 ; OPT-NEXT: [[TMP8]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP7]], i64 [[PHI_BROKEN]])
32 ; OPT-NEXT: [[TMP9:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP8]])
33 ; OPT-NEXT: [[TMP10]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP6]], i64 [[PHI_BROKEN2]])
34 ; OPT-NEXT: br i1 [[TMP9]], label [[FLOW1]], label [[LOOP]]
35 ; OPT: Flow1:
36 ; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP8]])
37 ; OPT-NEXT: [[TMP11:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP10]])
38 ; OPT-NEXT: br i1 [[TMP11]], label [[IF:%.*]], label [[LOOP_OUTER]]
39 ; OPT: IF:
40 ; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP10]])
41 ; OPT-NEXT: ret void
42 ; OPT: ENDIF:
43 ; OPT-NEXT: [[TMP47]] = add i32 [[TMP45]], 1
44 ; OPT-NEXT: [[TMP51]] = icmp eq i32 [[TMP47]], [[CONT:%.*]]
45 ; OPT-NEXT: [[TMP51_INV]] = xor i1 [[TMP51]], true
46 ; OPT-NEXT: br label [[FLOW]]
115 ; OPT-LABEL: @multi_if_break_loop(
116 ; OPT-NEXT: bb:
117 ; OPT-NEXT: [[ID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
118 ; OPT-NEXT: [[TMP:%.*]] = sub i32 [[ID]], [[ARG:%.*]]
119 ; OPT-NEXT: br label [[BB1:%.*]]
120 ; OPT: bb1:
121 ; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP2:%.*]], [[FLOW4:%.*]] ], [ 0, [[BB:%.*]] ]
122 ; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[LSR_IV_NEXT:%.*]], [[FLOW4]] ]
123 ; OPT-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
124 ; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
125 ; OPT-NEXT: [[LOAD0:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
126 ; OPT-NEXT: br label [[NODEBLOCK:%.*]]
127 ; OPT: NodeBlock:
128 ; OPT-NEXT: [[PIVOT:%.*]] = icmp sge i32 [[LOAD0]], 1
129 ; OPT-NEXT: br i1 [[PIVOT]], label [[LEAFBLOCK1:%.*]], label [[FLOW:%.*]]
130 ; OPT: LeafBlock1:
131 ; OPT-NEXT: [[SWITCHLEAF2:%.*]] = icmp eq i32 [[LOAD0]], 1
132 ; OPT-NEXT: br i1 [[SWITCHLEAF2]], label [[CASE1:%.*]], label [[FLOW3:%.*]]
133 ; OPT: Flow3:
134 ; OPT-NEXT: [[TMP0:%.*]] = phi i1 [ [[CMP2:%.*]], [[CASE1]] ], [ true, [[LEAFBLOCK1]] ]
135 ; OPT-NEXT: br label [[FLOW]]
136 ; OPT: LeafBlock:
137 ; OPT-NEXT: [[SWITCHLEAF:%.*]] = icmp eq i32 [[LOAD0]], 0
138 ; OPT-NEXT: br i1 [[SWITCHLEAF]], label [[CASE0:%.*]], label [[FLOW5:%.*]]
139 ; OPT: Flow4:
140 ; OPT-NEXT: [[TMP1:%.*]] = phi i1 [ [[TMP6:%.*]], [[FLOW5]] ], [ [[TMP4:%.*]], [[FLOW]] ]
141 ; OPT-NEXT: [[TMP2]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP1]], i64 [[PHI_BROKEN]])
142 ; OPT-NEXT: [[TMP3:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP2]])
143 ; OPT-NEXT: br i1 [[TMP3]], label [[BB9:%.*]], label [[BB1]]
144 ; OPT: case0:
145 ; OPT-NEXT: [[LOAD1:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
146 ; OPT-NEXT: [[CMP1:%.*]] = icmp sge i32 [[TMP]], [[LOAD1]]
147 ; OPT-NEXT: br label [[FLOW5]]
148 ; OPT: Flow:
149 ; OPT-NEXT: [[TMP4]] = phi i1 [ [[TMP0]], [[FLOW3]] ], [ true, [[NODEBLOCK]] ]
150 ; OPT-NEXT: [[TMP5:%.*]] = phi i1 [ false, [[FLOW3]] ], [ true, [[NODEBLOCK]] ]
151 ; OPT-NEXT: br i1 [[TMP5]], label [[LEAFBLOCK:%.*]], label [[FLOW4]]
152 ; OPT: case1:
153 ; OPT-NEXT: [[LOAD2:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
154 ; OPT-NEXT: [[CMP2]] = icmp sge i32 [[TMP]], [[LOAD2]]
155 ; OPT-NEXT: br label [[FLOW3]]
156 ; OPT: Flow5:
157 ; OPT-NEXT: [[TMP6]] = phi i1 [ [[CMP1]], [[CASE0]] ], [ [[TMP4]], [[LEAFBLOCK]] ]
158 ; OPT-NEXT: br label [[FLOW4]]
159 ; OPT: bb9:
160 ; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]])
161 ; OPT-NEXT: ret void