1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
3; RUN: opt -S -mtriple=amdgcn-- -structurizecfg -si-annotate-control-flow < %s | FileCheck -check-prefix=OPT %s
4; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
5
6; Ensure two if.break calls, for both the inner and outer loops
7; FIXME: duplicate comparison
8define amdgpu_vs void @multi_else_break(<4 x float> %vec, i32 %ub, i32 %cont) {
9; OPT-LABEL: @multi_else_break(
10; OPT-NEXT:  main_body:
11; OPT-NEXT:    br label [[LOOP_OUTER:%.*]]
12; OPT:       LOOP.outer:
13; OPT-NEXT:    [[PHI_BROKEN2:%.*]] = phi i64 [ [[TMP10:%.*]], [[FLOW1:%.*]] ], [ 0, [[MAIN_BODY:%.*]] ]
14; OPT-NEXT:    [[TMP43:%.*]] = phi i32 [ 0, [[MAIN_BODY]] ], [ [[TMP4:%.*]], [[FLOW1]] ]
15; OPT-NEXT:    br label [[LOOP:%.*]]
16; OPT:       LOOP:
17; OPT-NEXT:    [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP8:%.*]], [[FLOW:%.*]] ], [ 0, [[LOOP_OUTER]] ]
18; OPT-NEXT:    [[TMP0:%.*]] = phi i32 [ undef, [[LOOP_OUTER]] ], [ [[TMP4]], [[FLOW]] ]
19; OPT-NEXT:    [[TMP45:%.*]] = phi i32 [ [[TMP43]], [[LOOP_OUTER]] ], [ [[TMP5:%.*]], [[FLOW]] ]
20; OPT-NEXT:    [[TMP48:%.*]] = icmp slt i32 [[TMP45]], [[UB:%.*]]
21; OPT-NEXT:    [[TMP1:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP48]])
22; OPT-NEXT:    [[TMP2:%.*]] = extractvalue { i1, i64 } [[TMP1]], 0
23; OPT-NEXT:    [[TMP3:%.*]] = extractvalue { i1, i64 } [[TMP1]], 1
24; OPT-NEXT:    br i1 [[TMP2]], label [[ENDIF:%.*]], label [[FLOW]]
25; OPT:       Flow:
26; OPT-NEXT:    [[TMP4]] = phi i32 [ [[TMP47:%.*]], [[ENDIF]] ], [ [[TMP0]], [[LOOP]] ]
27; OPT-NEXT:    [[TMP5]] = phi i32 [ [[TMP47]], [[ENDIF]] ], [ undef, [[LOOP]] ]
28; OPT-NEXT:    [[TMP6:%.*]] = phi i1 [ [[TMP51:%.*]], [[ENDIF]] ], [ true, [[LOOP]] ]
29; OPT-NEXT:    [[TMP7:%.*]] = phi i1 [ [[TMP51_INV:%.*]], [[ENDIF]] ], [ true, [[LOOP]] ]
30; OPT-NEXT:    call void @llvm.amdgcn.end.cf.i64(i64 [[TMP3]])
31; OPT-NEXT:    [[TMP8]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP7]], i64 [[PHI_BROKEN]])
32; OPT-NEXT:    [[TMP9:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP8]])
33; OPT-NEXT:    [[TMP10]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP6]], i64 [[PHI_BROKEN2]])
34; OPT-NEXT:    br i1 [[TMP9]], label [[FLOW1]], label [[LOOP]]
35; OPT:       Flow1:
36; OPT-NEXT:    call void @llvm.amdgcn.end.cf.i64(i64 [[TMP8]])
37; OPT-NEXT:    [[TMP11:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP10]])
38; OPT-NEXT:    br i1 [[TMP11]], label [[IF:%.*]], label [[LOOP_OUTER]]
39; OPT:       IF:
40; OPT-NEXT:    call void @llvm.amdgcn.end.cf.i64(i64 [[TMP10]])
41; OPT-NEXT:    ret void
42; OPT:       ENDIF:
43; OPT-NEXT:    [[TMP47]] = add i32 [[TMP45]], 1
44; OPT-NEXT:    [[TMP51]] = icmp eq i32 [[TMP47]], [[CONT:%.*]]
45; OPT-NEXT:    [[TMP51_INV]] = xor i1 [[TMP51]], true
46; OPT-NEXT:    br label [[FLOW]]
47;
48; GCN-LABEL: multi_else_break:
49; GCN:       ; %bb.0: ; %main_body
50; GCN-NEXT:    s_mov_b64 s[0:1], 0
51; GCN-NEXT:    v_mov_b32_e32 v0, 0
52; GCN-NEXT:    s_branch .LBB0_2
53; GCN-NEXT:  .LBB0_1: ; %loop.exit.guard
54; GCN-NEXT:    ; in Loop: Header=BB0_2 Depth=1
55; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
56; GCN-NEXT:    s_and_b64 s[2:3], exec, s[2:3]
57; GCN-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
58; GCN-NEXT:    s_andn2_b64 exec, exec, s[0:1]
59; GCN-NEXT:    s_cbranch_execz .LBB0_6
60; GCN-NEXT:  .LBB0_2: ; %LOOP.outer
61; GCN-NEXT:    ; =>This Loop Header: Depth=1
62; GCN-NEXT:    ; Child Loop BB0_4 Depth 2
63; GCN-NEXT:    ; implicit-def: $sgpr6_sgpr7
64; GCN-NEXT:    ; implicit-def: $sgpr2_sgpr3
65; GCN-NEXT:    s_mov_b64 s[4:5], 0
66; GCN-NEXT:    s_branch .LBB0_4
67; GCN-NEXT:  .LBB0_3: ; %Flow
68; GCN-NEXT:    ; in Loop: Header=BB0_4 Depth=2
69; GCN-NEXT:    s_or_b64 exec, exec, s[8:9]
70; GCN-NEXT:    s_and_b64 s[8:9], exec, s[6:7]
71; GCN-NEXT:    s_or_b64 s[4:5], s[8:9], s[4:5]
72; GCN-NEXT:    s_andn2_b64 exec, exec, s[4:5]
73; GCN-NEXT:    s_cbranch_execz .LBB0_1
74; GCN-NEXT:  .LBB0_4: ; %LOOP
75; GCN-NEXT:    ; Parent Loop BB0_2 Depth=1
76; GCN-NEXT:    ; => This Inner Loop Header: Depth=2
77; GCN-NEXT:    v_cmp_lt_i32_e32 vcc, v0, v4
78; GCN-NEXT:    s_or_b64 s[2:3], s[2:3], exec
79; GCN-NEXT:    s_or_b64 s[6:7], s[6:7], exec
80; GCN-NEXT:    s_and_saveexec_b64 s[8:9], vcc
81; GCN-NEXT:    s_cbranch_execz .LBB0_3
82; GCN-NEXT:  ; %bb.5: ; %ENDIF
83; GCN-NEXT:    ; in Loop: Header=BB0_4 Depth=2
84; GCN-NEXT:    v_add_i32_e32 v0, vcc, 1, v0
85; GCN-NEXT:    s_andn2_b64 s[2:3], s[2:3], exec
86; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, v5, v0
87; GCN-NEXT:    s_andn2_b64 s[6:7], s[6:7], exec
88; GCN-NEXT:    s_and_b64 s[10:11], vcc, exec
89; GCN-NEXT:    s_or_b64 s[6:7], s[6:7], s[10:11]
90; GCN-NEXT:    s_branch .LBB0_3
91; GCN-NEXT:  .LBB0_6: ; %IF
92; GCN-NEXT:    s_endpgm
93main_body:
94  br label %LOOP.outer
95
96LOOP.outer:                                       ; preds = %ENDIF, %main_body
97  %tmp43 = phi i32 [ 0, %main_body ], [ %tmp47, %ENDIF ]
98  br label %LOOP
99
100LOOP:                                             ; preds = %ENDIF, %LOOP.outer
101  %tmp45 = phi i32 [ %tmp43, %LOOP.outer ], [ %tmp47, %ENDIF ]
102  %tmp48 = icmp slt i32 %tmp45, %ub
103  br i1 %tmp48, label %ENDIF, label %IF
104
105IF:                                               ; preds = %LOOP
106  ret void
107
108ENDIF:                                            ; preds = %LOOP
109  %tmp47 = add i32 %tmp45, 1
110  %tmp51 = icmp eq i32 %tmp47, %cont
111  br i1 %tmp51, label %LOOP, label %LOOP.outer
112}
113
114define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 {
115; OPT-LABEL: @multi_if_break_loop(
116; OPT-NEXT:  bb:
117; OPT-NEXT:    [[ID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
118; OPT-NEXT:    [[TMP:%.*]] = sub i32 [[ID]], [[ARG:%.*]]
119; OPT-NEXT:    br label [[BB1:%.*]]
120; OPT:       bb1:
121; OPT-NEXT:    [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP2:%.*]], [[FLOW4:%.*]] ], [ 0, [[BB:%.*]] ]
122; OPT-NEXT:    [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[LSR_IV_NEXT:%.*]], [[FLOW4]] ]
123; OPT-NEXT:    [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
124; OPT-NEXT:    [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
125; OPT-NEXT:    [[LOAD0:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
126; OPT-NEXT:    br label [[NODEBLOCK:%.*]]
127; OPT:       NodeBlock:
128; OPT-NEXT:    [[PIVOT:%.*]] = icmp sge i32 [[LOAD0]], 1
129; OPT-NEXT:    br i1 [[PIVOT]], label [[LEAFBLOCK1:%.*]], label [[FLOW:%.*]]
130; OPT:       LeafBlock1:
131; OPT-NEXT:    [[SWITCHLEAF2:%.*]] = icmp eq i32 [[LOAD0]], 1
132; OPT-NEXT:    br i1 [[SWITCHLEAF2]], label [[CASE1:%.*]], label [[FLOW3:%.*]]
133; OPT:       Flow3:
134; OPT-NEXT:    [[TMP0:%.*]] = phi i1 [ [[CMP2:%.*]], [[CASE1]] ], [ true, [[LEAFBLOCK1]] ]
135; OPT-NEXT:    br label [[FLOW]]
136; OPT:       LeafBlock:
137; OPT-NEXT:    [[SWITCHLEAF:%.*]] = icmp eq i32 [[LOAD0]], 0
138; OPT-NEXT:    br i1 [[SWITCHLEAF]], label [[CASE0:%.*]], label [[FLOW5:%.*]]
139; OPT:       Flow4:
140; OPT-NEXT:    [[TMP1:%.*]] = phi i1 [ [[TMP6:%.*]], [[FLOW5]] ], [ [[TMP4:%.*]], [[FLOW]] ]
141; OPT-NEXT:    [[TMP2]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP1]], i64 [[PHI_BROKEN]])
142; OPT-NEXT:    [[TMP3:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP2]])
143; OPT-NEXT:    br i1 [[TMP3]], label [[BB9:%.*]], label [[BB1]]
144; OPT:       case0:
145; OPT-NEXT:    [[LOAD1:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
146; OPT-NEXT:    [[CMP1:%.*]] = icmp sge i32 [[TMP]], [[LOAD1]]
147; OPT-NEXT:    br label [[FLOW5]]
148; OPT:       Flow:
149; OPT-NEXT:    [[TMP4]] = phi i1 [ [[TMP0]], [[FLOW3]] ], [ true, [[NODEBLOCK]] ]
150; OPT-NEXT:    [[TMP5:%.*]] = phi i1 [ false, [[FLOW3]] ], [ true, [[NODEBLOCK]] ]
151; OPT-NEXT:    br i1 [[TMP5]], label [[LEAFBLOCK:%.*]], label [[FLOW4]]
152; OPT:       case1:
153; OPT-NEXT:    [[LOAD2:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
154; OPT-NEXT:    [[CMP2]] = icmp sge i32 [[TMP]], [[LOAD2]]
155; OPT-NEXT:    br label [[FLOW3]]
156; OPT:       Flow5:
157; OPT-NEXT:    [[TMP6]] = phi i1 [ [[CMP1]], [[CASE0]] ], [ [[TMP4]], [[LEAFBLOCK]] ]
158; OPT-NEXT:    br label [[FLOW4]]
159; OPT:       bb9:
160; OPT-NEXT:    call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]])
161; OPT-NEXT:    ret void
162;
163; GCN-LABEL: multi_if_break_loop:
164; GCN:       ; %bb.0: ; %bb
165; GCN-NEXT:    s_load_dword s2, s[0:1], 0x9
166; GCN-NEXT:    s_mov_b64 s[0:1], 0
167; GCN-NEXT:    s_mov_b32 s3, 0xf000
168; GCN-NEXT:    s_waitcnt lgkmcnt(0)
169; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
170; GCN-NEXT:    s_mov_b32 s2, -1
171; GCN-NEXT:    s_branch .LBB1_2
172; GCN-NEXT:  .LBB1_1: ; %Flow4
173; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=1
174; GCN-NEXT:    s_and_b64 s[4:5], exec, s[4:5]
175; GCN-NEXT:    s_or_b64 s[0:1], s[4:5], s[0:1]
176; GCN-NEXT:    s_andn2_b64 exec, exec, s[0:1]
177; GCN-NEXT:    s_cbranch_execz .LBB1_9
178; GCN-NEXT:  .LBB1_2: ; %bb1
179; GCN-NEXT:    ; =>This Inner Loop Header: Depth=1
180; GCN-NEXT:    buffer_load_dword v1, off, s[0:3], 0 glc
181; GCN-NEXT:    s_waitcnt vmcnt(0)
182; GCN-NEXT:    v_readfirstlane_b32 s8, v1
183; GCN-NEXT:    s_mov_b64 s[4:5], -1
184; GCN-NEXT:    s_cmp_lt_i32 s8, 1
185; GCN-NEXT:    s_mov_b64 s[6:7], -1
186; GCN-NEXT:    s_cbranch_scc1 .LBB1_6
187; GCN-NEXT:  ; %bb.3: ; %LeafBlock1
188; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=1
189; GCN-NEXT:    s_cmp_eq_u32 s8, 1
190; GCN-NEXT:    s_mov_b64 s[4:5], -1
191; GCN-NEXT:    s_cbranch_scc0 .LBB1_5
192; GCN-NEXT:  ; %bb.4: ; %case1
193; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=1
194; GCN-NEXT:    buffer_load_dword v1, off, s[0:3], 0 glc
195; GCN-NEXT:    s_waitcnt vmcnt(0)
196; GCN-NEXT:    v_cmp_ge_i32_e32 vcc, v0, v1
197; GCN-NEXT:    s_orn2_b64 s[4:5], vcc, exec
198; GCN-NEXT:  .LBB1_5: ; %Flow3
199; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=1
200; GCN-NEXT:    s_mov_b64 s[6:7], 0
201; GCN-NEXT:  .LBB1_6: ; %Flow
202; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=1
203; GCN-NEXT:    s_and_b64 vcc, exec, s[6:7]
204; GCN-NEXT:    s_cbranch_vccz .LBB1_1
205; GCN-NEXT:  ; %bb.7: ; %LeafBlock
206; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=1
207; GCN-NEXT:    s_cmp_eq_u32 s8, 0
208; GCN-NEXT:    s_cbranch_scc0 .LBB1_1
209; GCN-NEXT:  ; %bb.8: ; %case0
210; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=1
211; GCN-NEXT:    buffer_load_dword v1, off, s[0:3], 0 glc
212; GCN-NEXT:    s_waitcnt vmcnt(0)
213; GCN-NEXT:    v_cmp_ge_i32_e32 vcc, v0, v1
214; GCN-NEXT:    s_andn2_b64 s[4:5], s[4:5], exec
215; GCN-NEXT:    s_and_b64 s[6:7], vcc, exec
216; GCN-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
217; GCN-NEXT:    s_branch .LBB1_1
218; GCN-NEXT:  .LBB1_9: ; %bb9
219; GCN-NEXT:    s_endpgm
220bb:
221  %id = call i32 @llvm.amdgcn.workitem.id.x()
222  %tmp = sub i32 %id, %arg
223  br label %bb1
224
225bb1:
226  %lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %case0 ], [ %lsr.iv.next, %case1 ]
227  %lsr.iv.next = add i32 %lsr.iv, 1
228  %cmp0 = icmp slt i32 %lsr.iv.next, 0
229  %load0 = load volatile i32, i32 addrspace(1)* undef, align 4
230  switch i32 %load0, label %bb9 [
231  i32 0, label %case0
232  i32 1, label %case1
233  ]
234
235case0:
236  %load1 = load volatile i32, i32 addrspace(1)* undef, align 4
237  %cmp1 = icmp slt i32 %tmp, %load1
238  br i1 %cmp1, label %bb1, label %bb9
239
240case1:
241  %load2 = load volatile i32, i32 addrspace(1)* undef, align 4
242  %cmp2 = icmp slt i32 %tmp, %load2
243  br i1 %cmp2, label %bb1, label %bb9
244
245bb9:
246  ret void
247}
248
249declare i32 @llvm.amdgcn.workitem.id.x() #1
250
251attributes #0 = { nounwind }
252attributes #1 = { nounwind readnone }
253