Lines Matching refs:OPT
1 … -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s
7 ; OPT-LABEL: @break_loop(
8 ; OPT-NEXT: bb:
9 ; OPT-NEXT: [[ID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
10 ; OPT-NEXT: [[MY_TMP:%.*]] = sub i32 [[ID]], [[ARG:%.*]]
11 ; OPT-NEXT: br label [[BB1:%.*]]
12 ; OPT: bb1:
13 ; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP2:%.*]], [[FLOW:%.*]] ], [ 0, [[BB:%.*]] ]
14 ; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[LSR_IV_NEXT:%.*]], [[FLOW]] ]
15 ; OPT-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
16 ; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
17 ; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
18 ; OPT: bb4:
19 ; OPT-NEXT: [[LOAD:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
20 ; OPT-NEXT: [[CMP1:%.*]] = icmp sge i32 [[MY_TMP]], [[LOAD]]
21 ; OPT-NEXT: br label [[FLOW]]
22 ; OPT: Flow:
23 ; OPT-NEXT: [[TMP1:%.*]] = phi i1 [ [[CMP1]], [[BB4]] ], [ true, [[BB1]] ]
24 ; OPT-NEXT: [[TMP2]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP1]], i64 [[PHI_BROKEN]])
25 ; OPT-NEXT: [[TMP3:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP2]])
26 ; OPT-NEXT: br i1 [[TMP3]], label [[BB9:%.*]], label [[BB1]]
27 ; OPT: bb9:
28 ; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]])
29 ; OPT-NEXT: ret void
84 ; OPT-LABEL: @undef_phi_cond_break_loop(
85 ; OPT-NEXT: bb:
86 ; OPT-NEXT: [[ID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
87 ; OPT-NEXT: [[MY_TMP:%.*]] = sub i32 [[ID]], [[ARG:%.*]]
88 ; OPT-NEXT: br label [[BB1:%.*]]
89 ; OPT: bb1:
90 ; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP0:%.*]], [[FLOW:%.*]] ], [ 0, [[BB:%.*]] ]
91 ; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[LSR_IV_NEXT:%.*]], [[FLOW]] ]
92 ; OPT-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
93 ; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
94 ; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
95 ; OPT: bb4:
96 ; OPT-NEXT: [[LOAD:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
97 ; OPT-NEXT: [[CMP1:%.*]] = icmp sge i32 [[MY_TMP]], [[LOAD]]
98 ; OPT-NEXT: br label [[FLOW]]
99 ; OPT: Flow:
100 ; OPT-NEXT: [[MY_TMP3:%.*]] = phi i1 [ [[CMP1]], [[BB4]] ], [ undef, [[BB1]] ]
101 ; OPT-NEXT: [[TMP0]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[MY_TMP3]], i64 [[PHI_BROKEN]])
102 ; OPT-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP0]])
103 ; OPT-NEXT: br i1 [[TMP1]], label [[BB9:%.*]], label [[BB1]]
104 ; OPT: bb9:
105 ; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP0]])
106 ; OPT-NEXT: store volatile i32 7, i32 addrspace(3)* undef
107 ; OPT-NEXT: ret void
175 ; OPT-LABEL: @constexpr_phi_cond_break_loop(
176 ; OPT-NEXT: bb:
177 ; OPT-NEXT: [[ID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
178 ; OPT-NEXT: [[MY_TMP:%.*]] = sub i32 [[ID]], [[ARG:%.*]]
179 ; OPT-NEXT: br label [[BB1:%.*]]
180 ; OPT: bb1:
181 ; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP0:%.*]], [[FLOW:%.*]] ], [ 0, [[BB:%.*]] ]
182 ; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[LSR_IV_NEXT:%.*]], [[FLOW]] ]
183 ; OPT-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
184 ; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
185 ; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
186 ; OPT: bb4:
187 ; OPT-NEXT: [[LOAD:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
188 ; OPT-NEXT: [[CMP1:%.*]] = icmp sge i32 [[MY_TMP]], [[LOAD]]
189 ; OPT-NEXT: br label [[FLOW]]
190 ; OPT: Flow:
191 ; OPT-NEXT: [[MY_TMP3:%.*]] = phi i1 [ [[CMP1]], [[BB4]] ], [ icmp ne (i32 addrspace(3)* inttopt…
192 ; OPT-NEXT: [[TMP0]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[MY_TMP3]], i64 [[PHI_BROKEN]])
193 ; OPT-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP0]])
194 ; OPT-NEXT: br i1 [[TMP1]], label [[BB9:%.*]], label [[BB1]]
195 ; OPT: bb9:
196 ; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP0]])
197 ; OPT-NEXT: store volatile i32 7, i32 addrspace(3)* undef
198 ; OPT-NEXT: ret void
263 ; OPT-LABEL: @true_phi_cond_break_loop(
264 ; OPT-NEXT: bb:
265 ; OPT-NEXT: [[ID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
266 ; OPT-NEXT: [[MY_TMP:%.*]] = sub i32 [[ID]], [[ARG:%.*]]
267 ; OPT-NEXT: br label [[BB1:%.*]]
268 ; OPT: bb1:
269 ; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP0:%.*]], [[FLOW:%.*]] ], [ 0, [[BB:%.*]] ]
270 ; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[LSR_IV_NEXT:%.*]], [[FLOW]] ]
271 ; OPT-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
272 ; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
273 ; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
274 ; OPT: bb4:
275 ; OPT-NEXT: [[LOAD:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
276 ; OPT-NEXT: [[CMP1:%.*]] = icmp sge i32 [[MY_TMP]], [[LOAD]]
277 ; OPT-NEXT: br label [[FLOW]]
278 ; OPT: Flow:
279 ; OPT-NEXT: [[MY_TMP3:%.*]] = phi i1 [ [[CMP1]], [[BB4]] ], [ true, [[BB1]] ]
280 ; OPT-NEXT: [[TMP0]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[MY_TMP3]], i64 [[PHI_BROKEN]])
281 ; OPT-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP0]])
282 ; OPT-NEXT: br i1 [[TMP1]], label [[BB9:%.*]], label [[BB1]]
283 ; OPT: bb9:
284 ; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP0]])
285 ; OPT-NEXT: store volatile i32 7, i32 addrspace(3)* undef
286 ; OPT-NEXT: ret void
351 ; OPT-LABEL: @false_phi_cond_break_loop(
352 ; OPT-NEXT: bb:
353 ; OPT-NEXT: [[ID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
354 ; OPT-NEXT: [[MY_TMP:%.*]] = sub i32 [[ID]], [[ARG:%.*]]
355 ; OPT-NEXT: br label [[BB1:%.*]]
356 ; OPT: bb1:
357 ; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP0:%.*]], [[FLOW:%.*]] ], [ 0, [[BB:%.*]] ]
358 ; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[LSR_IV_NEXT:%.*]], [[FLOW]] ]
359 ; OPT-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
360 ; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
361 ; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
362 ; OPT: bb4:
363 ; OPT-NEXT: [[LOAD:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
364 ; OPT-NEXT: [[CMP1:%.*]] = icmp sge i32 [[MY_TMP]], [[LOAD]]
365 ; OPT-NEXT: br label [[FLOW]]
366 ; OPT: Flow:
367 ; OPT-NEXT: [[MY_TMP3:%.*]] = phi i1 [ [[CMP1]], [[BB4]] ], [ false, [[BB1]] ]
368 ; OPT-NEXT: [[TMP0]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[MY_TMP3]], i64 [[PHI_BROKEN]])
369 ; OPT-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP0]])
370 ; OPT-NEXT: br i1 [[TMP1]], label [[BB9:%.*]], label [[BB1]]
371 ; OPT: bb9:
372 ; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP0]])
373 ; OPT-NEXT: store volatile i32 7, i32 addrspace(3)* undef
374 ; OPT-NEXT: ret void
442 ; OPT-LABEL: @invert_true_phi_cond_break_loop(
443 ; OPT-NEXT: bb:
444 ; OPT-NEXT: [[ID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
445 ; OPT-NEXT: [[MY_TMP:%.*]] = sub i32 [[ID]], [[ARG:%.*]]
446 ; OPT-NEXT: br label [[BB1:%.*]]
447 ; OPT: bb1:
448 ; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP1:%.*]], [[FLOW:%.*]] ], [ 0, [[BB:%.*]] ]
449 ; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[LSR_IV_NEXT:%.*]], [[FLOW]] ]
450 ; OPT-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
451 ; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
452 ; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
453 ; OPT: bb4:
454 ; OPT-NEXT: [[LOAD:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
455 ; OPT-NEXT: [[CMP1:%.*]] = icmp sge i32 [[MY_TMP]], [[LOAD]]
456 ; OPT-NEXT: br label [[FLOW]]
457 ; OPT: Flow:
458 ; OPT-NEXT: [[MY_TMP3:%.*]] = phi i1 [ [[CMP1]], [[BB4]] ], [ true, [[BB1]] ]
459 ; OPT-NEXT: [[TMP0:%.*]] = xor i1 [[MY_TMP3]], true
460 ; OPT-NEXT: [[TMP1]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP0]], i64 [[PHI_BROKEN]])
461 ; OPT-NEXT: [[TMP2:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP1]])
462 ; OPT-NEXT: br i1 [[TMP2]], label [[BB9:%.*]], label [[BB1]]
463 ; OPT: bb9:
464 ; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP1]])
465 ; OPT-NEXT: store volatile i32 7, i32 addrspace(3)* undef
466 ; OPT-NEXT: ret void