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Searched refs:NumLanes (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ShuffleDecode.cpp150 unsigned NumLanes = Size / 128; in DecodePSHUFMask() local
151 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodePSHUFMask()
152 unsigned NumLaneElts = NumElts / NumLanes; in DecodePSHUFMask()
222 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodeUNPCKHMask()
223 unsigned NumLaneElts = NumElts / NumLanes; in DecodeUNPCKHMask()
238 if (NumLanes == 0 ) NumLanes = 1; // Handle MMX in DecodeUNPCKLMask()
239 unsigned NumLaneElts = NumElts / NumLanes; in DecodeUNPCKLMask()
480 unsigned NumLanes = VecSize / 128; in DecodeVPERMILPMask() local
481 unsigned NumEltsPerLane = NumElts / NumLanes; in DecodeVPERMILPMask()
502 unsigned NumLanes = VecSize / 128; in DecodeVPERMIL2PMask() local
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.cpp311 unsigned NumLanes = Size / 4; in allocateSGPRSpillToVGPR() local
313 if (NumLanes > WaveSize) in allocateSGPRSpillToVGPR()
321 for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) { in allocateSGPRSpillToVGPR()
386 unsigned NumLanes = Size / 4; in allocateVGPRSpillToAGPR() local
387 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
415 for (int I = NumLanes - 1; I >= 0; --I) { in allocateVGPRSpillToAGPR()
H A DAMDGPURegisterBankInfo.cpp1967 unsigned NumLanes = DstRegs.size(); in foldExtractEltToCmpSelect() local
1968 if (!NumLanes) in foldExtractEltToCmpSelect()
1969 NumLanes = 1; in foldExtractEltToCmpSelect()
1974 SmallVector<Register, 2> Res(NumLanes); in foldExtractEltToCmpSelect()
1975 for (unsigned L = 0; L < NumLanes; ++L) in foldExtractEltToCmpSelect()
1984 for (unsigned L = 0; L < NumLanes; ++L) { in foldExtractEltToCmpSelect()
1995 for (unsigned L = 0; L < NumLanes; ++L) { in foldExtractEltToCmpSelect()
2068 unsigned NumLanes = InsRegs.size(); in foldInsertEltToCmpSelect() local
2069 if (!NumLanes) { in foldInsertEltToCmpSelect()
2070 NumLanes = 1; in foldInsertEltToCmpSelect()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp2271 int NumLanes = 1; in addConstantComments() local
2274 case X86::VBROADCASTF128: NumLanes = 2; break; in addConstantComments()
2275 case X86::VBROADCASTI128: NumLanes = 2; break; in addConstantComments()
2276 case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break; in addConstantComments()
2277 case X86::VBROADCASTF32X4rm: NumLanes = 4; break; in addConstantComments()
2278 case X86::VBROADCASTF32X8rm: NumLanes = 2; break; in addConstantComments()
2279 case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break; in addConstantComments()
2280 case X86::VBROADCASTF64X2rm: NumLanes = 4; break; in addConstantComments()
2281 case X86::VBROADCASTF64X4rm: NumLanes = 2; break; in addConstantComments()
2296 for (int l = 0; l != NumLanes; ++l) { in addConstantComments()
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H A DX86InstCombineIntrinsic.cpp448 unsigned NumLanes = ResTy->getPrimitiveSizeInBits() / 128; in simplifyX86pack() local
453 unsigned NumSrcEltsPerLane = NumSrcElts / NumLanes; in simplifyX86pack()
491 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyX86pack()
1966 unsigned NumLanes = Ty0->getPrimitiveSizeInBits() / 128; in simplifyDemandedVectorEltsIntrinsic() local
1967 unsigned VWidthPerLane = VWidth / NumLanes; in simplifyDemandedVectorEltsIntrinsic()
1968 unsigned InnerVWidthPerLane = InnerVWidth / NumLanes; in simplifyDemandedVectorEltsIntrinsic()
1976 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyDemandedVectorEltsIntrinsic()
1991 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyDemandedVectorEltsIntrinsic()
H A DX86InterleavedAccess.cpp481 unsigned NumLanes = std::max((int)VT.getSizeInBits() / 128, 1); in DecodePALIGNRMask() local
482 unsigned NumLaneElts = NumElts / NumLanes; in DecodePALIGNRMask()
H A DX86ISelLowering.cpp7567 int NumLanes = VT.getSizeInBits() / 128; in getPackDemandedElts() local
7570 int NumEltsPerLane = NumElts / NumLanes; in getPackDemandedElts()
7592 int NumLanes = VT.getSizeInBits() / 128; in getHorizDemandedElts() local
7594 int NumEltsPerLane = NumElts / NumLanes; in getHorizDemandedElts()
11656 if (NumLanes > 1) { in isMultiLaneShuffleMask()
11657 for (int i = 0; i != NumLanes; ++i) { in isMultiLaneShuffleMask()
13012 int NumLaneElts = NumElts / NumLanes; in lowerShuffleAsUNPCKAndPermute()
14053 int NumLanes = Bits / 128; in lowerShuffleAsZeroOrAnyExtend() local
17445 int NumLaneElts = NumElts / NumLanes; in lowerShuffleAsRepeatedMaskAndLanePermute()
23129 unsigned NumLanes = BitWidth / 128; in lowerAddSubToHorizontalOp() local
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.h158 template <unsigned NumLanes, char LaneKind>
H A DAArch64InstPrinter.cpp1429 template <unsigned NumLanes, char LaneKind>
1434 if (NumLanes) in printTypedVectorList()
1435 Suffix += itostr(NumLanes) + LaneKind; in printTypedVectorList()
/llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp1064 : DL(DL), SE(SE), R(R), NumLanes(NumLanes), MaxLevel(MaxLevel) {} in LookAheadHeuristics()
1150 if (std::abs(*Dist) > NumLanes / 2) in getShallowScore()
1190 if (std::abs(Dist) > NumLanes / 2) in getShallowScore()
1402 for (unsigned Lane = 0, NumLanes = getNumLanes(); Lane != NumLanes; in clearUsed() local
1741 unsigned NumLanes = VL.size(); in appendOperandsOfVL() local
1743 OpsVec[OpIdx].resize(NumLanes); in appendOperandsOfVL()
1832 unsigned NumLanes = getNumLanes(); in reorder() local
2341 unsigned NumLanes = Scalars.size(); in setOperandsInOrder() local
2344 Operands[OpIdx].resize(NumLanes); in setOperandsInOrder()
4399 unsigned NumLanes = TE->Scalars.size(); in findExternalStoreUsersReorderIndices() local
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H A DLoopVectorize.cpp2869 Value *NumLanes = getRuntimeVF(Builder, Ty, VF * UF); in getOrCreateVectorTripCount() local
2871 TC, Builder.CreateSub(NumLanes, ConstantInt::get(Ty, 1)), "n.rnd.up"); in getOrCreateVectorTripCount()
/llvm-project-15.0.7/clang/utils/TableGen/
H A DNeonEmitter.cpp767 unsigned NumLanes; in fromTypedefName() local
768 Name.substr(0, I).getAsInteger(10, NumLanes); in fromTypedefName()
770 T.Bitwidth = T.ElementBitwidth * NumLanes; in fromTypedefName()
/llvm-project-15.0.7/llvm/lib/IR/
H A DAutoUpgrade.cpp2626 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128; in UpgradeIntrinsicCall() local
2628 unsigned ControlBitsMask = NumLanes - 1; in UpgradeIntrinsicCall()
2629 unsigned NumControlBits = NumLanes / 2; in UpgradeIntrinsicCall()
2632 for (unsigned l = 0; l != NumLanes; ++l) { in UpgradeIntrinsicCall()
2635 if (l >= NumLanes / 2) in UpgradeIntrinsicCall()
2636 LaneMask += NumLanes; in UpgradeIntrinsicCall()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2362 size_t NumLanes = Op.getSimpleValueType().getVectorNumElements(); in unrollVectorShift() local
2370 for (size_t i = 0; i < NumLanes; ++i) { in unrollVectorShift()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrInfo.td728 class MVEVectorIndexOperand<int NumLanes> : AsmOperandClass {
729 let Name = "MVEVectorIndex"#NumLanes;
731 let PredicateMethod = "isVectorIndexInRange<"#NumLanes#">";
734 class MVEVectorIndex<int NumLanes> : Operand<i32> {
736 let ParserMatchClass = MVEVectorIndexOperand<NumLanes>;
H A DARMISelLowering.cpp16708 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVCVTCombine() local
16709 if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) { in PerformVCVTCombine()
16728 ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVCVTCombine()
16809 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVDIVCombine() local
16810 if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) { in PerformVDIVCombine()
16829 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVDIVCombine()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuiltin.cpp13678 unsigned NumLanes = Ty->getPrimitiveSizeInBits() / 128; in EmitX86BuiltinExpr() local
13679 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
13704 unsigned NumLanes = Ty->getPrimitiveSizeInBits() / 128; in EmitX86BuiltinExpr() local
13705 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
13811 unsigned NumLanes = Ty->getPrimitiveSizeInBits() == 512 ? 4 : 2; in EmitX86BuiltinExpr() local
13812 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
13816 unsigned Index = (Imm % NumLanes) * NumLaneElts; in EmitX86BuiltinExpr()
13817 Imm /= NumLanes; // Discard the bits we just used. in EmitX86BuiltinExpr()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp14565 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in performFDivCombine() local
14566 switch (NumLanes) { in performFDivCombine()
19777 uint64_t NumLanes = ResVT.getVectorElementCount().getKnownMinValue(); in PerformDAGCombine() local
19778 SDValue ExtIdx = DAG.getVectorIdxConstant(IdxConst * NumLanes, DL); in PerformDAGCombine()
19794 uint64_t NumLanes = in PerformDAGCombine() local
19797 if ((TupleLanes % NumLanes) != 0) in PerformDAGCombine()
19800 uint64_t NumVecs = TupleLanes / NumLanes; in PerformDAGCombine()
19807 SDValue ExtIdx = DAG.getVectorIdxConstant(I * NumLanes, DL); in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2225 template <unsigned NumLanes>
2228 return VectorIndex.Val < NumLanes; in isVectorIndexInRange()