| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 72 const TargetRegisterClass *NewRC = in constrainRegClass() local
74 if (!NewRC || NewRC == OldRC) in constrainRegClass()
75 return NewRC; in constrainRegClass()
76 if (NewRC->getNumRegs() < MinNumRegs) in constrainRegClass()
78 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
79 return NewRC; in constrainRegClass()
123 const TargetRegisterClass *NewRC = in recomputeRegClass() local
127 if (NewRC == OldRC) in recomputeRegClass()
135 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, in recomputeRegClass()
137 if (!NewRC || NewRC == OldRC) in recomputeRegClass()
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| H A D | CriticalAntiDepBreaker.cpp | 186 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction() local
189 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in PrescanInstruction()
193 if (!Classes[Reg] && NewRC) in PrescanInstruction()
194 Classes[Reg] = NewRC; in PrescanInstruction()
195 else if (!NewRC || Classes[Reg] != NewRC) in PrescanInstruction()
321 const TargetRegisterClass *NewRC = nullptr; in ScanInstruction() local
323 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in ScanInstruction()
327 if (!Classes[Reg] && NewRC) in ScanInstruction()
328 Classes[Reg] = NewRC; in ScanInstruction()
329 else if (!NewRC || Classes[Reg] != NewRC) in ScanInstruction()
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| H A D | RegisterCoalescer.h | 57 const TargetRegisterClass *NewRC = nullptr; variable
81 bool isPhys() const { return !NewRC; } in isPhys()
109 const TargetRegisterClass *getNewRC() const { return NewRC; } in getNewRC()
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| H A D | RegisterCoalescer.cpp | 460 NewRC = nullptr; in setRegisters()
508 if (!NewRC) in setRegisters()
513 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
520 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
524 if (!NewRC) in setRegisters()
535 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1371 const TargetRegisterClass *NewRC = CP.getNewRC(); in reMaterializeTrivialDef() local
1381 NewRC = CommonRC; in reMaterializeTrivialDef()
1430 NewRC = TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx); in reMaterializeTrivialDef()
1432 NewRC = TRI->getCommonSubClass(NewRC, DefRC); in reMaterializeTrivialDef()
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| H A D | TailDuplicator.cpp | 443 auto *NewRC = MI->getRegClassConstraint(i, TII, TRI); in duplicateInstruction() local
444 if (NewRC == nullptr) in duplicateInstruction()
445 NewRC = OrigRC; in duplicateInstruction()
446 Register NewReg = MRI->createVirtualRegister(NewRC); in duplicateInstruction()
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| H A D | PeepholeOptimizer.cpp | 781 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI() local
785 Register NewVR = MRI.createVirtualRegister(NewRC); in insertPHI()
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | LazyCallGraph.cpp | 1639 RefSCC *NewRC = OriginalRC; in addSplitFunction() local
1651 NewRC->SCCs.insert(NewRC->SCCs.begin() + InsertIndex, NewC); in addSplitFunction()
1653 NewRC->SCCIndices[NewRC->SCCs[I]] = I; in addSplitFunction()
1666 NewRC->SCCIndices[NewC] = 0; in addSplitFunction()
1667 NewRC->SCCs.push_back(NewC); in addSplitFunction()
1713 RefSCC *NewRC; in addSplitRefRecursiveFunctions() local
1718 NewRC = OriginalRC; in addSplitRefRecursiveFunctions()
1721 NewRC = createRefSCC(*this); in addSplitRefRecursiveFunctions()
1743 NewRC->SCCs.push_back(NewC); in addSplitRefRecursiveFunctions()
1938 buildSCCs(*NewRC, Nodes); in buildRefSCCs()
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| H A D | CGSCCPassManager.cpp | 1071 for (RefSCC *NewRC : llvm::reverse(llvm::drop_begin(NewRefSCCs))) { in updateCGAndAnalysisManagerForPass()
1072 assert(NewRC != RC && "Should not encounter the current RefSCC further " in updateCGAndAnalysisManagerForPass()
1074 UR.RCWorklist.insert(NewRC); in updateCGAndAnalysisManagerForPass()
1076 << *NewRC << "\n"); in updateCGAndAnalysisManagerForPass()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.cpp | 296 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
297 if (this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) { in shouldCoalesce()
302 NewRC, LIS); in shouldCoalesce()
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| H A D | AVRRegisterInfo.h | 56 unsigned DstSubReg, const TargetRegisterClass *NewRC,
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 384 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
389 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) && in shouldCoalesce()
435 if (NewRC->contains(*SI)) { in shouldCoalesce()
444 if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128)) in shouldCoalesce()
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| H A D | SystemZRegisterInfo.h | 173 const TargetRegisterClass *NewRC,
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.h | 61 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
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| H A D | HexagonVLIWPacketizer.h | 146 bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
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| H A D | HexagonRegisterInfo.cpp | 350 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
357 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID()) in shouldCoalesce()
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| H A D | HexagonFrameLowering.cpp | 2247 const TargetRegisterClass *NewRC) -> const TargetRegisterClass * { in optimizeSpillSlots() argument
2248 if (HaveRC == nullptr || HaveRC == NewRC) in optimizeSpillSlots()
2249 return NewRC; in optimizeSpillSlots()
2251 if (HaveRC->hasSubClassEq(NewRC)) in optimizeSpillSlots()
2253 if (NewRC->hasSubClassEq(HaveRC)) in optimizeSpillSlots()
2254 return NewRC; in optimizeSpillSlots()
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| H A D | HexagonBitSimplify.cpp | 2653 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
2655 NewRC[I] = BitTracker::BitValue(C & 1); in simplifyRCmp0()
2658 BT.put(BitTracker::RegisterRef(NewR), NewRC); in simplifyRCmp0()
2721 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
2722 NewRC[0] = BitTracker::BitValue::self(); in simplifyRCmp0()
2723 NewRC.fill(1, W, BitTracker::BitValue::Zero); in simplifyRCmp0()
2724 BT.put(BitTracker::RegisterRef(NewR), NewRC); in simplifyRCmp0()
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| H A D | HexagonVLIWPacketizer.cpp | 360 const TargetRegisterClass *NewRC) { in isNewifiable() argument
363 if (NewRC == &Hexagon::PredRegsRegClass) { in isNewifiable()
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| H A D | HexagonConstPropagation.cpp | 2898 const TargetRegisterClass *NewRC; in rewriteHexConstDefs() local
2905 NewRC = &Hexagon::IntRegsRegClass; in rewriteHexConstDefs()
2907 NewRC = &Hexagon::DoubleRegsRegClass; in rewriteHexConstDefs()
2908 Register NewR = MRI->createVirtualRegister(NewRC); in rewriteHexConstDefs()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.h | 136 unsigned DstSubReg, const TargetRegisterClass *NewRC,
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| H A D | AArch64RegisterInfo.cpp | 859 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 237 const TargetRegisterClass *NewRC,
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| H A D | ARMBaseRegisterInfo.cpp | 882 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
892 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && in shouldCoalesce()
897 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); in shouldCoalesce()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 306 const TargetRegisterClass *NewRC,
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 1041 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
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