| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3542 bool LegalOps; member
3548 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} in TargetLoweringOpt()
3551 bool LegalOperations() const { return LegalOps; } in LegalOperations()
3954 bool LegalOps, bool OptForSize,
3961 bool LegalOps, bool OptForSize,
3965 getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth);
3976 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
3979 return getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth);
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2152 if (DemandedBits.isOne() && !TLO.LegalOps && !VT.isVector()) in SimplifyDemandedBits()
3224 if (Updated && !IdentityLHS && !IdentityRHS && !TLO.LegalOps) { in SimplifyDemandedVectorElts()
6710 if (LegalOps && !IsOpLegal) in getNegatedExpression()
6740 if (LegalOps && !IsOpLegal) in getNegatedExpression()
6761 if (LegalOps && !isOperationLegalOrCustom(ISD::FSUB, VT)) in getNegatedExpression()
6768 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
6776 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
6824 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
6832 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
6869 getNegatedExpression(Z, DAG, LegalOps, OptForSize, CostZ, Depth); in getNegatedExpression()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 819 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
|
| H A D | PPCISelLowering.cpp | 16855 bool LegalOps, bool OptForSize, in getNegatedExpression() argument
16878 getNegatedExpression(N2, DAG, LegalOps, OptForSize, N2Cost, Depth + 1); in getNegatedExpression()
16890 SDValue NegN0 = getNegatedExpression(N0, DAG, LegalOps, OptForSize, in getNegatedExpression()
16894 SDValue NegN1 = getNegatedExpression(N1, DAG, LegalOps, OptForSize, in getNegatedExpression()
16915 return TargetLowering::getNegatedExpression(Op, DAG, LegalOps, OptForSize, in getNegatedExpression()
17353 bool LegalOps = !DCI.isBeforeLegalizeOps(); in combineFMALike() local
17366 if (SDValue NegN0 = getCheaperNegatedExpression(N0, DAG, LegalOps, CodeSize)) in combineFMALike()
17371 if (SDValue NegN1 = getCheaperNegatedExpression(N1, DAG, LegalOps, CodeSize)) in combineFMALike()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 929 if (Op.getOpcode() == ISD::BUILD_VECTOR && TLO.LegalOps && TLO.LegalTys) in shouldSimplifyDemandedVectorElts()
|
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 9438 if (!TLO.LegalOps) in targetShrinkDemandedConstant()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1833 if (!TLO.LegalOps) in targetShrinkDemandedConstant()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 19899 if (!TLO.LegalOps) in targetShrinkDemandedConstant()
|