Lines Matching refs:LegalOps
2152 if (DemandedBits.isOne() && !TLO.LegalOps && !VT.isVector()) in SimplifyDemandedBits()
3224 if (Updated && !IdentityLHS && !IdentityRHS && !TLO.LegalOps) { in SimplifyDemandedVectorElts()
6661 bool LegalOps, bool OptForSize, in getNegatedExpression() argument
6710 if (LegalOps && !IsOpLegal) in getNegatedExpression()
6740 if (LegalOps && !IsOpLegal) in getNegatedExpression()
6761 if (LegalOps && !isOperationLegalOrCustom(ISD::FSUB, VT)) in getNegatedExpression()
6768 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
6776 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
6824 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
6832 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
6869 getNegatedExpression(Z, DAG, LegalOps, OptForSize, CostZ, Depth); in getNegatedExpression()
6880 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
6888 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
6915 if (SDValue NegV = getNegatedExpression(Op.getOperand(0), DAG, LegalOps, in getNegatedExpression()
6920 if (SDValue NegV = getNegatedExpression(Op.getOperand(0), DAG, LegalOps, in getNegatedExpression()