| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetCallingConv.h | 29 unsigned IsZExt : 1; ///< Zero extended
63 : IsZExt(0), IsSExt(0), IsInReg(0), IsSRet(0), IsByVal(0), IsByRef(0), in ArgFlagsTy()
73 bool isZExt() const { return IsZExt; } in isZExt()
74 void setZExt() { IsZExt = 1; } in setZExt()
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| H A D | MachineFrameInfo.h | 532 void setObjectZExt(int ObjectIdx, bool IsZExt) { in setObjectZExt() argument
535 Objects[ObjectIdx+NumFixedObjects].isZExt = IsZExt; in setObjectZExt()
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| H A D | TargetLowering.h | 288 bool IsZExt : 1; variable
305 : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false), in ArgListEntry()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 310 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) in isIntExtFree()
3940 if (IsZExt) { in emiti1Ext()
4189 if (!IsZExt) { in emitLSR_ri()
4195 IsZExt = true; in emitLSR_ri()
4456 if (!(IsZExt && isZExtLoad(LoadMI)) && !(!IsZExt && isSExtLoad(LoadMI))) in optimizeIntExtLoad()
4465 if (IsZExt) { in optimizeIntExtLoad()
4507 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) { in selectIntExt()
4591 bool IsZExt = true; in selectMul() local
4597 IsZExt = true; in selectMul()
4661 IsZExt = true; in selectShift()
[all …]
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| H A D | AArch64ISelLowering.cpp | 4086 Entry.IsZExt = false; in LowerFSINCOS()
13819 bool IsZExt = false; in performVecReduceAddCombineWithUADDLP() local
13821 IsZExt = true; in performVecReduceAddCombineWithUADDLP()
13823 IsZExt = false; in performVecReduceAddCombineWithUADDLP()
13844 SDValue UABDHigh8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
13855 SDValue UABDLo8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 844 Imm = (IsZExt) ? (int64_t)CIVal.getZExtValue() : in PPCEmitCmp()
846 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) in PPCEmitCmp()
919 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; in PPCEmitCmp()
921 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI; in PPCEmitCmp()
925 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD; in PPCEmitCmp()
927 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI; in PPCEmitCmp()
1816 if (!IsZExt) { in PPCEmitIntExt()
1906 bool IsZExt = isa<ZExtInst>(I); in SelectIntExt() local
2309 bool IsZExt = false; in tryToFoldLoadIntoMI() local
2316 IsZExt = true; in tryToFoldLoadIntoMI()
[all …]
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| H A D | PPCISelLowering.cpp | 17844 Entry.IsZExt = !Entry.IsSExt; in lowerToLibCall()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 186 bool IsZExt);
1751 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet() local
1752 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
1889 unsigned DestReg, bool IsZExt) { in emitIntExt() argument
1897 if (IsZExt) in emitIntExt()
1976 bool IsZExt = Opcode == Instruction::LShr; in selectShift() local
1977 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt)) in selectShift()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 2029 Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned); in ExpandLibCall()
2187 Entry.IsZExt = !isSigned; in ExpandDivRemLibCall()
2196 Entry.IsZExt = !isSigned; in ExpandDivRemLibCall()
2279 Entry.IsZExt = false; in ExpandSinCosLibCall()
2287 Entry.IsZExt = false; in ExpandSinCosLibCall()
2295 Entry.IsZExt = false; in ExpandSinCosLibCall()
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| H A D | LegalizeIntegerTypes.cpp | 4075 Entry.IsZExt = false; in ExpandExtIntRes_DIVREM()
4084 Entry.IsZExt = false; in ExpandExtIntRes_DIVREM()
4095 Entry.IsZExt = true; in ExpandExtIntRes_DIVREM()
4467 Entry.IsZExt = false; in ExpandIntRes_XMULO()
4475 Entry.IsZExt = false; in ExpandIntRes_XMULO()
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| H A D | FastISel.cpp | 1038 if (Arg.IsZExt) in lowerCallTo()
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| H A D | SelectionDAGBuilder.cpp | 9682 Entry.IsZExt = false; in LowerCallTo()
9784 if (Args[i].IsZExt) in LowerCallTo()
9863 else if (Args[i].IsZExt) in LowerCallTo()
9887 CLI.RetZExt == Args[i].IsZExt)) in LowerCallTo()
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| H A D | TargetLowering.cpp | 112 IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt); in setAttributes()
161 Entry.IsZExt = !Entry.IsSExt; in makeLibCall()
165 Entry.IsSExt = Entry.IsZExt = false; in makeLibCall()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 501 Entry.IsZExt = !IsSigned; in LowerDivRem()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9801 Entry.IsZExt = false; in LowerFSINCOS()
9811 Entry.IsZExt = false; in LowerFSINCOS()
20408 Entry.IsZExt = !isSigned; in getDivRemArgList()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 1900 Entry.IsZExt = !shouldSignExtendTypeInLibCall(Op.getValueType(), IsSigned); in makeExternalCall()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 29505 Entry.IsZExt = false; in LowerWin64_i128OP()
31847 Entry.IsZExt = false; in LowerFSINCOS()
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