Lines Matching refs:IsZExt
162 const TargetRegisterClass *RC, bool IsZExt = true,
169 unsigned DestReg, bool IsZExt);
452 bool IsZExt, unsigned FP64LoadOpc) { in PPCEmitLoad() argument
481 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8) in PPCEmitLoad()
485 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8) in PPCEmitLoad()
819 bool IsZExt, unsigned DestReg, in PPCEmitCmp() argument
844 Imm = (IsZExt) ? (int64_t)CIVal.getZExtValue() : in PPCEmitCmp()
846 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) in PPCEmitCmp()
919 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; in PPCEmitCmp()
921 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI; in PPCEmitCmp()
925 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD; in PPCEmitCmp()
927 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI; in PPCEmitCmp()
933 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
939 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
1809 unsigned DestReg, bool IsZExt) { in PPCEmitIntExt() argument
1816 if (!IsZExt) { in PPCEmitIntExt()
1906 bool IsZExt = isa<ZExtInst>(I); in SelectIntExt() local
1932 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt)) in SelectIntExt()
2309 bool IsZExt = false; in tryToFoldLoadIntoMI() local
2316 IsZExt = true; in tryToFoldLoadIntoMI()
2327 IsZExt = true; in tryToFoldLoadIntoMI()
2365 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt, in tryToFoldLoadIntoMI()