| /llvm-project-15.0.7/llvm/include/llvm/Support/ |
| H A D | LowLevelTypeImpl.h | 112 : IsScalar(false), IsPointer(false), IsVector(false), RawData(0) {} in LLT()
120 bool isPointer() const { return isValid() && IsPointer && !IsVector; } in isPointer()
122 bool isVector() const { return isValid() && IsVector; } in isVector()
227 if (IsVector) { in getScalarSizeInBits()
241 if (!IsVector) in getAddressSpace()
266 return IsPointer == RHS.IsPointer && IsVector == RHS.IsVector &&
335 uint64_t IsVector : 1;
358 this->IsVector = IsVector;
362 else if (IsVector) {
387 ((uint64_t)IsPointer) << 1 | ((uint64_t)IsVector);
[all …]
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| /llvm-project-15.0.7/clang-tools-extra/clang-tidy/portability/ |
| H A D | SIMDIntrinsicsCheck.cpp | 30 bool IsVector = Node.getReturnType()->isVectorType(); in AST_MATCHER() local
36 IsVector = true; in AST_MATCHER()
38 return IsVector; in AST_MATCHER()
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| /llvm-project-15.0.7/llvm/lib/Support/ |
| H A D | LowLevelType.cpp | 32 IsVector = false; in LLT()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600ExpandSpecialInstrs.cpp | 164 bool IsVector = TII->isVector(MI); in runOnMachineFunction() local
166 if (!IsReduction && !IsVector && !IsCube) { in runOnMachineFunction()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 489 bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
494 int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP);
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| H A D | MachineIRBuilder.h | 690 bool IsVector,
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMELFStreamer.cpp | 1399 const SmallVectorImpl<unsigned> &RegList, bool IsVector, in collectHWRegs() argument
1408 assert(Reg < (IsVector ? 32U : 16U) && "Register out of range"); in collectHWRegs()
1422 bool IsVector) { in emitRegSave() argument
1435 std::tie(Idx, Count) = collectHWRegs(MRI, Idx, RegList, IsVector, Mask); in emitRegSave()
1441 SPOffset -= Count * (IsVector ? 8 : 4); in emitRegSave()
1445 if (IsVector) in emitRegSave()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 1273 bool llvm::isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, in isConstTrueVal() argument
1275 switch (TLI.getBooleanContents(IsVector, IsFP)) { in isConstTrueVal()
1286 int64_t llvm::getICmpTrueVal(const TargetLowering &TLI, bool IsVector, in getICmpTrueVal() argument
1288 switch (TLI.getBooleanContents(IsVector, IsFP)) { in getICmpTrueVal()
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| H A D | MachineIRBuilder.cpp | 478 bool IsVector, in buildBoolExtInReg() argument
481 switch (TLI->getBooleanContents(IsVector, IsFP)) { in buildBoolExtInReg()
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| H A D | CombinerHelper.cpp | 2903 int64_t Cst, bool IsVector, bool IsFP) { in isConstValidTrue() argument
2906 isConstTrueVal(TLI, Cst, IsVector, IsFP); in isConstValidTrue()
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| /llvm-project-15.0.7/llvm/include/llvm/AsmParser/ |
| H A D | LLParser.h | 413 bool parseArrayVectorType(Type *&Result, bool IsVector);
|
| /llvm-project-15.0.7/llvm/lib/AsmParser/ |
| H A D | LLParser.cpp | 2847 bool LLParser::parseArrayVectorType(Type *&Result, bool IsVector) { in parseArrayVectorType() argument
2850 if (IsVector && Lex.getKind() == lltok::kw_vscale) { in parseArrayVectorType()
2874 if (parseToken(IsVector ? lltok::greater : lltok::rsquare, in parseArrayVectorType()
2878 if (IsVector) { in parseArrayVectorType()
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| /llvm-project-15.0.7/clang/lib/CodeGen/ |
| H A D | CGExpr.cpp | 1850 bool IsVector = true) { in MaybeConvertMatrixAddress() argument
1852 if (ArrayTy && IsVector) { in MaybeConvertMatrixAddress()
1859 if (VectorTy && !IsVector) { in MaybeConvertMatrixAddress()
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| H A D | TargetInfo.cpp | 7590 bool IsVector = false; in EmitVAArg() local
7600 IsVector = ArgTy->isVectorTy(); in EmitVAArg()
7605 if (IsVector && UnpaddedSize > PaddedSize) in EmitVAArg()
7615 if (IsVector) { in EmitVAArg()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 479 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
11718 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) { in parseDirectiveRegSave() argument
11732 if (!IsVector && !Op.isRegList()) in parseDirectiveRegSave()
11734 if (IsVector && !Op.isDPRRegList()) in parseDirectiveRegSave()
11737 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector); in parseDirectiveRegSave()
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| /llvm-project-15.0.7/clang/docs/ |
| H A D | InternalsManual.rst | 1795 bool IsVector;
|