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Searched refs:IsAdd (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Support/
H A DDivisionByConstantInfo.cpp70 Retval.IsAdd = false; // initialize "add" indicator in get()
92 Retval.IsAdd = true; in get()
97 Retval.IsAdd = true; in get()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp452 unsigned Reg, int NumBytes, bool IsAdd, in emitRegUpdate() argument
456 Opc = IsAdd ? ARC::ADD_rru6 : ARC::SUB_rru6; in emitRegUpdate()
458 Opc = IsAdd ? ARC::ADD_rrs12 : ARC::SUB_rrs12; in emitRegUpdate()
460 Opc = IsAdd ? ARC::ADD_rrlimm : ARC::SUB_rrlimm; in emitRegUpdate()
484 bool IsAdd = (Old.getOpcode() == ARC::ADJCALLSTACKUP); in eliminateCallFramePseudoInstr() local
485 emitRegUpdate(MBB, I, dl, ARC::SP, Amt, IsAdd, TII); in eliminateCallFramePseudoInstr()
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DDivisionByConstantInfo.h32 bool IsAdd; ///< add indicator member
/llvm-project-15.0.7/llvm/unittests/Support/
H A DKnownBitsTest.cpp52 static void TestAddSubExhaustive(bool IsAdd) { in TestAddSubExhaustive() argument
66 if (IsAdd) in TestAddSubExhaustive()
82 KnownBits::computeForAddSub(IsAdd, /*NSW*/ false, Known1, Known2); in TestAddSubExhaustive()
88 IsAdd, /*NSW*/true, Known1, Known2); in TestAddSubExhaustive()
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DLoopFlatten.cpp198 bool IsAdd = match(U, m_c_Add(m_Specific(InnerInductionPHI), in matchLinearIVUser() local
216 if (Widened && IsAdd && in matchLinearIVUser()
225 if ((IsAdd || IsAddTrunc) && MatchedItCount == InnerTripCount) { in matchLinearIVUser()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp838 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE; in SelectADD_SUB_I64() local
861 unsigned Opc = OpcMap[0][N->isDivergent()][IsAdd]; in SelectADD_SUB_I64()
862 unsigned CarryOpc = OpcMap[1][N->isDivergent()][IsAdd]; in SelectADD_SUB_I64()
922 bool IsAdd = N->getOpcode() == ISD::UADDO; in SelectUADDO_USUBO() local
928 if ((IsAdd && (UI->getOpcode() != ISD::ADDCARRY)) || in SelectUADDO_USUBO()
929 (!IsAdd && (UI->getOpcode() != ISD::SUBCARRY))) { in SelectUADDO_USUBO()
936 unsigned Opc = IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64; in SelectUADDO_USUBO()
H A DAMDGPUInstructionSelector.cpp412 const bool IsAdd = I.getOpcode() == AMDGPU::G_UADDO || in selectG_UADDO_USUBO_UADDE_USUBE() local
419 IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64; in selectG_UADDO_USUBO_UADDE_USUBE()
420 unsigned CarryOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64; in selectG_UADDO_USUBO_UADDE_USUBE()
435 unsigned NoCarryOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32; in selectG_UADDO_USUBO_UADDE_USUBE()
436 unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32; in selectG_UADDO_USUBO_UADDE_USUBE()
H A DSIISelLowering.cpp4022 bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO); in EmitInstrWithCustomInserter() local
4024 unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32; in EmitInstrWithCustomInserter()
4025 unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32; in EmitInstrWithCustomInserter()
4043 bool IsAdd = (MI.getOpcode() == AMDGPU::V_ADD_U64_PSEUDO); in EmitInstrWithCustomInserter() local
4049 if (IsAdd && ST.hasLshlAddB64()) { in EmitInstrWithCustomInserter()
4090 unsigned LoOpc = IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64; in EmitInstrWithCustomInserter()
4097 unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64; in EmitInstrWithCustomInserter()
H A DSIInstrInfo.cpp6766 bool IsAdd = (Inst.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO); in splitScalar64BitAddSub() local
6801 unsigned LoOpc = IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64; in splitScalar64BitAddSub()
6809 unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64; in splitScalar64BitAddSub()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp6890 if (IsAdd) in lowerSADDO_SSUBO()
6922 bool IsAdd; in lowerAddSubSatToMinMax() local
6929 IsAdd = true; in lowerAddSubSatToMinMax()
6934 IsAdd = true; in lowerAddSubSatToMinMax()
6939 IsAdd = false; in lowerAddSubSatToMinMax()
6944 IsAdd = false; in lowerAddSubSatToMinMax()
6966 if (IsAdd) { in lowerAddSubSatToMinMax()
7000 bool IsAdd; in lowerAddSubSatToAddoSubo() local
7007 IsAdd = true; in lowerAddSubSatToAddoSubo()
7012 IsAdd = true; in lowerAddSubSatToAddoSubo()
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H A DCombinerHelper.cpp4810 if (magics.IsAdd && !Divisor[0]) { in buildUDivUsingMul()
4815 assert(!magics.IsAdd && "Should use cheap fixup now"); in buildUDivUsingMul()
4819 if (!magics.IsAdd || Divisor.isOneValue()) { in buildUDivUsingMul()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp5962 if (magics.IsAdd && !Divisor[0]) { in BuildUDIV()
5967 assert(!magics.IsAdd && "Should use cheap fixup now"); in BuildUDIV()
5971 if (!magics.IsAdd || Divisor.isOne()) { in BuildUDIV()
9216 bool IsAdd = Node->getOpcode() == ISD::UADDO; in expandUADDSUBO() local
9219 unsigned OpcCarry = IsAdd ? ISD::ADDCARRY : ISD::SUBCARRY; in expandUADDSUBO()
9229 Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl, in expandUADDSUBO()
9236 if (IsAdd && isOneConstant(RHS)) { in expandUADDSUBO()
9246 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT; in expandUADDSUBO()
9257 bool IsAdd = Node->getOpcode() == ISD::SADDO; in expandSADDSUBO() local
9259 Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl, in expandSADDSUBO()
[all …]
H A DDAGCombiner.cpp2331 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubBoolOfMaskedVal() local
2332 SDValue C = IsAdd ? N->getOperand(1) : N->getOperand(0); in foldAddSubBoolOfMaskedVal()
2333 SDValue Z = IsAdd ? N->getOperand(0) : N->getOperand(1); in foldAddSubBoolOfMaskedVal()
2371 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubOfSignBit() local
2372 SDValue ConstantOp = IsAdd ? N->getOperand(1) : N->getOperand(0); in foldAddSubOfSignBit()
2373 SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1); in foldAddSubOfSignBit()
2395 IsAdd ? ISD::ADD : ISD::SUB, DL, VT, in foldAddSubOfSignBit()
9348 bool IsAdd = N0.getOpcode() == ISD::ADD; in visitSRA() local
9349 SDValue Shl = N0.getOperand(IsAdd ? 0 : 1); in visitSRA()
9354 isConstOrConstSplat(N0.getOperand(IsAdd ? 1 : 0))) { in visitSRA()
[all …]
H A DLegalizeDAG.cpp3457 bool IsAdd = Node->getOpcode() == ISD::ADDCARRY; in ExpandNode() local
3460 unsigned Op = IsAdd ? ISD::ADD : ISD::SUB; in ExpandNode()
3467 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT; in ExpandNode()
3482 IsAdd ? DAG.getSetCC(dl, SetCCType, Sum2, Zero, ISD::SETEQ) in ExpandNode()
H A DLegalizeIntegerTypes.cpp3986 bool IsAdd = Node->getOpcode() == ISD::SADDO; in ExpandIntRes_SADDSUBO() local
3987 unsigned CarryOp = IsAdd ? ISD::SADDO_CARRY : ISD::SSUBO_CARRY; in ExpandIntRes_SADDSUBO()
3999 Lo = DAG.getNode(IsAdd ? ISD::UADDO : ISD::USUBO, dl, VTList, {LHSL, RHSL}); in ExpandIntRes_SADDSUBO()
4036 if (IsAdd) in ExpandIntRes_SADDSUBO()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp7032 bool IsAdd = N->getOpcode() == ISD::UADDO; in ReplaceNodeResults() local
7042 if (IsAdd && isOneConstant(RHS)) { in ReplaceNodeResults()
7056 IsAdd ? ISD::SETULT : ISD::SETUGT); in ReplaceNodeResults()
8269 bool IsAdd = N->getOpcode() == RISCVISD::ADD_VL; in combineADDSUB_VLToVWADDSUB_VL() local
8299 WOpc = IsAdd ? RISCVISD::VWADD_W_VL : RISCVISD::VWSUB_W_VL; in combineADDSUB_VLToVWADDSUB_VL()
8351 bool IsAdd = N->getOpcode() == RISCVISD::VWADD_W_VL || in combineVWADD_W_VL_VWSUB_W_VL() local
8356 if (IsAdd && Op0.getOpcode() == RISCVISD::VMV_V_X_VL && in combineVWADD_W_VL_VWSUB_W_VL()
8701 bool IsAdd = N0.getOpcode() == ISD::ADD; in performSRACombine() local
8702 if ((IsAdd || N0.getOpcode() == ISD::SUB)) { in performSRACombine()
8714 Shl = N0.getOperand(IsAdd ? 0 : 1); in performSRACombine()
[all …]
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DValueTracking.cpp1678 bool IsAdd = II->getIntrinsicID() == Intrinsic::uadd_sat; in computeKnownBitsFromOperator() local
1686 if (IsAdd) in computeKnownBitsFromOperator()
1694 IsAdd, /* NSW */ false, Known, Known2); in computeKnownBitsFromOperator()
1698 if (IsAdd) { in computeKnownBitsFromOperator()
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineSelect.cpp1851 auto IsSignedSaturateLimit = [&](Value *Limit, bool IsAdd) { in foldOverflowingAddSubSelect() argument
1872 if (IsAdd) { in foldOverflowingAddSubSelect()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1030 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; in performMADD_MSUBCombine() local
1031 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd) in performMADD_MSUBCombine()
/llvm-project-15.0.7/clang/lib/Sema/
H A DSemaOpenMP.cpp8259 bool IsAdd = BO->getOpcode() == BO_Add; in checkAndSetIncRHS() local
8261 return setStep(BO->getRHS(), !IsAdd); in checkAndSetIncRHS()
8262 if (IsAdd && getInitLCDecl(BO->getRHS()) == LCDecl) in checkAndSetIncRHS()
8266 bool IsAdd = CE->getOperator() == OO_Plus; in checkAndSetIncRHS() local
8267 if ((IsAdd || CE->getOperator() == OO_Minus) && CE->getNumArgs() == 2) { in checkAndSetIncRHS()
8269 return setStep(CE->getArg(1), !IsAdd); in checkAndSetIncRHS()
8270 if (IsAdd && getInitLCDecl(CE->getArg(1)) == LCDecl) in checkAndSetIncRHS()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp15915 static SDValue foldOverflowCheck(SDNode *Op, SelectionDAG &DAG, bool IsAdd) { in foldOverflowCheck() argument
15920 if (IsAdd) { in foldOverflowCheck()
15928 SDValue CsetOp = CmpOp->getOperand(IsAdd ? 0 : 1); in foldOverflowCheck()
15930 if (CC != (IsAdd ? AArch64CC::HS : AArch64CC::LO)) in foldOverflowCheck()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp17568 bool IsAdd = ((N.getOpcode() == ISD::ADD) || (N.getOpcode() == ISD::OR)); in setAlignFlagsForFI() local
17569 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(IsAdd ? N.getOperand(0) : N); in setAlignFlagsForFI()
17583 if (!IsAdd) { in setAlignFlagsForFI()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp31815 bool IsAdd = Opc == ISD::ADDCARRY || Opc == ISD::SADDO_CARRY; in LowerADDSUBCARRY() local
31816 SDValue Sum = DAG.getNode(IsAdd ? X86ISD::ADC : X86ISD::SBB, DL, VTs, in LowerADDSUBCARRY()
49852 bool IsAdd = (Opcode == ISD::FADD) || (Opcode == ISD::ADD); in combineToHorizontalAddSub() local
49862 auto HorizOpcode = IsAdd ? X86ISD::FHADD : X86ISD::FHSUB; in combineToHorizontalAddSub()
49863 if (isHorizontalBinOp(HorizOpcode, LHS, RHS, DAG, Subtarget, IsAdd, in combineToHorizontalAddSub()
49879 auto HorizOpcode = IsAdd ? X86ISD::HADD : X86ISD::HSUB; in combineToHorizontalAddSub()
49880 if (isHorizontalBinOp(HorizOpcode, LHS, RHS, DAG, Subtarget, IsAdd, in combineToHorizontalAddSub()