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Searched refs:IntrID (Results 1 – 21 of 21) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86LowerAMXIntrinsics.cpp80 template <Intrinsic::ID IntrID>
81 typename std::enable_if<IntrID == Intrinsic::x86_tdpbssd_internal ||
92 template <Intrinsic::ID IntrID>
93 typename std::enable_if<IntrID == Intrinsic::x86_tdpbssd_internal ||
237 template <Intrinsic::ID IntrID>
238 typename std::enable_if<IntrID == Intrinsic::x86_tdpbssd_internal ||
249 switch (IntrID) { in createTileDPLoops()
364 if (IntrID != Intrinsic::x86_tdpbf16ps_internal) { in createTileDPLoops()
388 switch (IntrID) { in createTileDPLoops()
471 template <Intrinsic::ID IntrID>
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/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DEarlyCSE.cpp682 switch (IntrID) { in ParseMemoryInst()
712 if (IntrID != 0) in isLoad()
718 if (IntrID != 0) in isStore()
724 if (IntrID != 0) in isAtomic()
730 if (IntrID != 0) in isUnordered()
743 if (IntrID != 0) in isVolatile()
768 if (IntrID != 0) in getMatchingId()
774 if (IntrID != 0) in getPointerOperand()
795 if (IntrID != 0) in mayReadFromMemory()
801 if (IntrID != 0) in mayWriteToMemory()
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H A DLoopIdiomRecognize.cpp2463 Intrinsic::ID IntrID = Intrinsic::ctlz; in recognizeShiftUntilBitTest() local
2474 IntrID, Ty, {UndefValue::get(Ty), /*is_zero_undef=*/Builder.getTrue()}); in recognizeShiftUntilBitTest()
2498 IntrID, Ty, {XMasked, /*is_zero_undef=*/Builder.getTrue()}, in recognizeShiftUntilBitTest()
2792 Intrinsic::ID IntrID; in recognizeShiftUntilZero() local
2797 if (!detectShiftUntilZeroIdiom(CurLoop, SE, ValShiftedIsZero, IntrID, IV, in recognizeShiftUntilZero()
2828 IntrID, Ty, {UndefValue::get(Ty), /*is_zero_undef=*/Builder.getFalse()}); in recognizeShiftUntilZero()
2846 IntrID, Ty, {Val, /*is_zero_undef=*/Builder.getFalse()}, in recognizeShiftUntilZero()
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DPatternMatch.h2045 IntrinsicID_match(Intrinsic::ID IntrID) : ID(IntrID) {} in IntrinsicID_match()
2098 return IntrinsicID_match(IntrID);
2117 template <Intrinsic::ID IntrID, typename T0>
2119 return m_CombineAnd(m_Intrinsic<IntrID>(), m_Argument<0>(Op0));
2122 template <Intrinsic::ID IntrID, typename T0, typename T1>
2125 return m_CombineAnd(m_Intrinsic<IntrID>(Op0), m_Argument<1>(Op1));
2128 template <Intrinsic::ID IntrID, typename T0, typename T1, typename T2>
2134 template <Intrinsic::ID IntrID, typename T0, typename T1, typename T2,
2141 template <Intrinsic::ID IntrID, typename T0, typename T1, typename T2,
2146 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2, Op3),
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H A DIRBuilder.h628 Intrinsic::ID IntrID, Value *Dst, MaybeAlign DstAlign, Value *Src,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUPromoteAlloca.cpp300 Intrinsic::ID IntrID = Intrinsic::not_intrinsic; in getWorkitemID() local
305 IntrID = IsAMDGCN ? (Intrinsic::ID)Intrinsic::amdgcn_workitem_id_x in getWorkitemID()
310 IntrID = IsAMDGCN ? (Intrinsic::ID)Intrinsic::amdgcn_workitem_id_y in getWorkitemID()
316 IntrID = IsAMDGCN ? (Intrinsic::ID)Intrinsic::amdgcn_workitem_id_z in getWorkitemID()
324 Function *WorkitemIdFn = Intrinsic::getDeclaration(Mod, IntrID); in getWorkitemID()
H A DAMDGPUISelDAGToDAG.cpp2346 unsigned Opc = IntrID == Intrinsic::amdgcn_ds_append ? in SelectDSAppendConsume()
2383 static unsigned gwsIntrinToOpcode(unsigned IntrID) { in gwsIntrinToOpcode() argument
2384 switch (IntrID) { in gwsIntrinToOpcode()
2402 void AMDGPUDAGToDAGISel::SelectDS_GWS(SDNode *N, unsigned IntrID) { in SelectDS_GWS() argument
2403 if (IntrID == Intrinsic::amdgcn_ds_gws_sema_release_all && in SelectDS_GWS()
2456 const unsigned Opc = gwsIntrinToOpcode(IntrID); in SelectDS_GWS()
2527 switch (IntrID) { in SelectINTRINSIC_W_CHAIN()
2532 SelectDSAppendConsume(N, IntrID); in SelectINTRINSIC_W_CHAIN()
2543 switch (IntrID) { in SelectINTRINSIC_WO_CHAIN()
2571 switch (IntrID) { in SelectINTRINSIC_VOID()
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H A DAMDGPUISelDAGToDAG.h266 void SelectDSAppendConsume(SDNode *N, unsigned IntrID);
267 void SelectDS_GWS(SDNode *N, unsigned IntrID);
H A DAMDGPUTargetTransformInfo.cpp971 auto IntrID = II->getIntrinsicID(); in rewriteIntrinsicWithAddressSpace() local
972 switch (IntrID) { in rewriteIntrinsicWithAddressSpace()
992 unsigned TrueAS = IntrID == Intrinsic::amdgcn_is_shared ? in rewriteIntrinsicWithAddressSpace()
H A DAMDGPULegalizerInfo.cpp4624 static unsigned getBufferAtomicPseudo(Intrinsic::ID IntrID) { in getBufferAtomicPseudo() argument
4625 switch (IntrID) { in getBufferAtomicPseudo()
5554 auto IntrID = MI.getIntrinsicID(); in legalizeIntrinsic() local
5555 switch (IntrID) { in legalizeIntrinsic()
5575 if (IntrID == Intrinsic::amdgcn_if) { in legalizeIntrinsic()
5769 return legalizeBufferAtomic(MI, B, IntrID); in legalizeIntrinsic()
5785 return legalizeBufferAtomic(MI, B, IntrID); in legalizeIntrinsic()
5800 return legalizeDSAtomicFPIntrinsic(Helper, MI, IntrID); in legalizeIntrinsic()
5805 AMDGPU::getImageDimIntrinsicInfo(IntrID)) in legalizeIntrinsic()
H A DAMDGPURegisterBankInfo.cpp3067 auto IntrID = MI.getIntrinsicID(); in applyMappingImpl() local
3068 switch (IntrID) { in applyMappingImpl()
3138 AMDGPU::lookupRsrcIntrinsic(IntrID)) { in applyMappingImpl()
4524 auto IntrID = MI.getIntrinsicID(); in getInstrMapping() local
4525 const AMDGPU::RsrcIntrinsic *RSrcIntrin = AMDGPU::lookupRsrcIntrinsic(IntrID); in getInstrMapping()
4553 auto IntrID = MI.getIntrinsicID(); in getInstrMapping() local
4554 switch (IntrID) { in getInstrMapping()
H A DSIISelLowering.cpp958 AMDGPU::lookupRsrcIntrinsic(IntrID)) { in getTgtMemIntrinsic()
982 = AMDGPU::getImageDimIntrinsicInfo(IntrID); in getTgtMemIntrinsic()
1025 switch (IntrID) { in getTgtMemIntrinsic()
1039 switch (IntrID) { in getTgtMemIntrinsic()
1152 if (IntrID == Intrinsic::amdgcn_ds_gws_barrier) in getTgtMemIntrinsic()
7205 switch (IntrID) { in LowerINTRINSIC_W_CHAIN()
7263 switch (IntrID) { in LowerINTRINSIC_W_CHAIN()
7279 switch (IntrID) { in LowerINTRINSIC_W_CHAIN()
7491 switch (IntrID) { in LowerINTRINSIC_W_CHAIN()
7826 switch (IntrID) { in LowerINTRINSIC_W_CHAIN()
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H A DAMDGPUInstructionSelector.cpp1314 MachineInstr &MI, Intrinsic::ID IntrID) const { in selectDSOrderedIntrinsic()
1343 unsigned Instruction = IntrID == Intrinsic::amdgcn_ds_ordered_add ? 0 : 1; in selectDSOrderedIntrinsic()
1377 static unsigned gwsIntrinToOpcode(unsigned IntrID) { in gwsIntrinToOpcode() argument
1378 switch (IntrID) { in gwsIntrinToOpcode()
H A DAMDGPUISelLowering.cpp710 unsigned IntrID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in isSDNodeAlwaysUniform() local
711 switch (IntrID) { in isSDNodeAlwaysUniform()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVEmitIntrinsics.cpp59 CallInst *buildIntrWithMD(Intrinsic::ID IntrID, ArrayRef<Type *> Types, in buildIntrWithMD() argument
64 return IRB->CreateIntrinsic(IntrID, {Types}, {Arg2, VMD}); in buildIntrWithMD()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineVerifier.cpp1439 unsigned IntrID = IntrIDOp.getIntrinsicID(); in verifyPreISelGenericInstruction() local
1440 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) { in verifyPreISelGenericInstruction()
1443 static_cast<Intrinsic::ID>(IntrID)); in verifyPreISelGenericInstruction()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h1009 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
H A DAMDGPUBaseInfo.cpp2387 bool isIntrinsicSourceOfDivergence(unsigned IntrID) { in isIntrinsicSourceOfDivergence() argument
2388 return lookupSourceOfDivergence(IntrID); in isIntrinsicSourceOfDivergence()
/llvm-project-15.0.7/llvm/lib/IR/
H A DIRBuilder.cpp225 Intrinsic::ID IntrID, Value *Dst, MaybeAlign DstAlign, Value *Src, in CreateMemTransferInst() argument
234 Function *TheFn = Intrinsic::getDeclaration(M, IntrID, Tys); in CreateMemTransferInst()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGExpr.cpp3608 llvm::CallInst *CodeGenFunction::EmitTrapCall(llvm::Intrinsic::ID IntrID) { in EmitTrapCall() argument
3610 Builder.CreateCall(CGM.getIntrinsic(IntrID)); in EmitTrapCall()
H A DCodeGenFunction.h4631 llvm::CallInst *EmitTrapCall(llvm::Intrinsic::ID IntrID);