Home
last modified time | relevance | path

Searched refs:Insn (Results 1 – 25 of 54) sorted by relevance

123

/llvm-project-15.0.7/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
64 Insn = in readInstruction32()
217 unsigned Combined = fieldFromInstruction(Insn, 6, 5); in Decode2OpInstruction()
220 if (fieldFromInstruction(Insn, 5, 1)) { in Decode2OpInstruction()
236 unsigned Combined = fieldFromInstruction(Insn, 6, 5); in Decode3OpInstruction()
253 unsigned Opcode = fieldFromInstruction(Insn, 11, 5); in Decode2OpInstructionFail()
323 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
416 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) | in DecodeL2OpInstructionFail()
645 unsigned Opcode = fieldFromInstruction(Insn, 27, 5); in DecodeL5RInstructionFail()
678 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp135 addr |= fieldFromInstruction(Insn, 0, 4); in decodeFIOARr()
148 addr |= fieldFromInstruction(Insn, 0, 4); in decodeFIORdA()
225 k |= fieldFromInstruction(Insn, 0, 4); in decodeFWRdK()
256 if (Insn > 127) in decodeMemri()
275 if ((Insn & 0xf000) == 0x8000) { in decodeLoadStore()
310 if ((Insn & 0xfc00) != 0x9000 || (Insn & 0xf) == 0) in decodeLoadStore()
315 switch (Insn & 0xc) { in decodeLoadStore()
330 switch (Insn & 0x203) { in decodeLoadStore()
381 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
395 Insn = in readInstruction32()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp54 Insn = in readInstruction32()
172 unsigned S9 = Insn & 0x1ff; in DecodeMEMrs9()
233 DstB = decodeBField(Insn); in DecodeStLImmInstruction()
238 SrcC = decodeCField(Insn); in DecodeStLImmInstruction()
240 LImm = (Insn >> 32); in DecodeStLImmInstruction()
251 SrcB = decodeBField(Insn); in DecodeLdLImmInstruction()
256 DstA = decodeAField(Insn); in DecodeLdLImmInstruction()
258 LImm = (Insn >> 32); in DecodeLdLImmInstruction()
269 DstA = decodeAField(Insn); in DecodeLdRLImmInstruction()
271 SrcB = decodeBField(Insn); in DecodeLdRLImmInstruction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp722 uint32_t Cond = (Insn >> 28) & 0xF; in checkDecodedInstruction()
798 uint32_t Insn = in getARMInstruction() local
2095 if (!fieldFromInstruction(Insn, 23, 1)) in DecodeAddrMode2IdxInstruction()
2802 fieldFromInstruction(Insn, 4,4) != 0) in DecodeSETPANInstruction()
2805 fieldFromInstruction(Insn, 0,4) != 0) in DecodeSETPANInstruction()
4775 if(!fieldFromInstruction(Insn, 7, 1)) { in DecodeMveAddrModeQ()
5261 if (fieldFromInstruction(Insn, 4, 1)) in DecodeVLD1LN()
5266 if (fieldFromInstruction(Insn, 5, 1)) in DecodeVLD1LN()
5269 if (fieldFromInstruction(Insn, 4, 1)) in DecodeVLD1LN()
5273 if (fieldFromInstruction(Insn, 6, 1)) in DecodeVLD1LN()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp84 Insn = in readInstruction32()
101 AluOp = (Insn >> 8) & 0x7; in PostOperandDecodeAdjust()
109 unsigned PQ = (Insn >> PqShift) & 0x3; in PostOperandDecodeAdjust()
135 uint32_t Insn; in getInstruction() local
147 PostOperandDecodeAdjust(Instr, Insn); in getInstruction()
179 unsigned Register = (Insn >> 18) & 0x1f; in decodeRiMemoryValue()
181 unsigned Offset = (Insn & 0xffff); in decodeRiMemoryValue()
192 unsigned Register = (Insn >> 15) & 0x1f; in decodeRrMemoryValue()
194 Register = (Insn >> 10) & 0x1f; in decodeRrMemoryValue()
207 unsigned Offset = (Insn & 0x3ff); in decodeSplsValue()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp1113 Insn = (Bytes[0] << 8) | Bytes[1]; in readInstruction16()
1115 Insn = (Bytes[1] << 8) | Bytes[0]; in readInstruction16()
1142 Insn = in readInstruction32()
1161 uint32_t Insn; in getInstruction() local
1667 unsigned Offset = Insn & 0xf; in DecodeMemMMImm4()
1724 unsigned Offset = Insn & 0x1F; in DecodeMemMMSPImm5Lsl2()
1739 unsigned Offset = Insn & 0x7F; in DecodeMemMMGPImm7Lsl2()
1761 Offset = SignExtend32<4>(Insn & 0xf); in DecodeMemMMReglistImm4Lsl2()
2253 int Size = (int) Insn - Pos + 1; in DecodeInsSize()
2275 switch (Insn) { in DecodeSimm9SP()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.cpp44 SmallVectorImpl<ImmInsnModel> &Insn) { in tryToreplicateChunks() argument
67 Insn.push_back({ AArch64::ORRXri, 0, Encoding }); in tryToreplicateChunks()
80 Insn.push_back({ AArch64::MOVKXi, Imm16, in tryToreplicateChunks()
95 Insn.push_back({ AArch64::MOVKXi, Imm16, in tryToreplicateChunks()
223 Insn.push_back({ AArch64::ORRXri, 0, Encoding }); in trySequenceOfOnes()
246 SmallVectorImpl<ImmInsnModel> &Insn) { in expandMOVImmSimple() argument
278 Insn.push_back({ FirstOpc, Imm16, in expandMOVImmSimple()
296 Insn.push_back({ Opc, Imm16, in expandMOVImmSimple()
330 Insn.push_back({ Opc, 0, Encoding }); in expandMOVImm()
369 Insn.push_back({ AArch64::MOVKXi, Imm16, in expandMOVImm()
[all …]
H A DAArch64MIPeepholeOpt.cpp127 SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn; in splitBitmaskImm() local
128 AArch64_IMM::expandMOVImm(UImm, RegSize, Insn); in splitBitmaskImm()
129 if (Insn.size() == 1) in splitBitmaskImm()
262 SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn; in splitAddSubImm() local
263 AArch64_IMM::expandMOVImm(Imm, RegSize, Insn); in splitAddSubImm()
264 if (Insn.size() == 1) in splitAddSubImm()
H A DAArch64ExpandImm.h29 SmallVectorImpl<ImmInsnModel> &Insn);
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DInstructionPrecedenceTracking.cpp63 const Instruction *Insn) { in isPreceededBySpecialInstruction() argument
65 getFirstSpecialInstruction(Insn->getParent()); in isPreceededBySpecialInstruction()
66 return MaybeFirstSpecial && MaybeFirstSpecial->comesBefore(Insn); in isPreceededBySpecialInstruction()
90 for (const Instruction &Insn : *BB) in validate()
91 if (isSpecialInstruction(&Insn)) { in validate()
92 assert(It->second == &Insn && in validate()
138 const Instruction *Insn) const { in isSpecialInstruction()
144 return !isGuaranteedToTransferExecutionToSuccessor(Insn); in isSpecialInstruction()
148 const Instruction *Insn) const { in isSpecialInstruction()
150 if (match(Insn, m_Intrinsic<Intrinsic::experimental_widenable_condition>())) in isSpecialInstruction()
[all …]
H A DGuardUtils.cpp35 for (auto &Insn : *DeoptBB) { in isGuardAsWidenableBranch()
36 if (match(&Insn, m_Intrinsic<Intrinsic::experimental_deoptimize>())) in isGuardAsWidenableBranch()
38 if (Insn.mayHaveSideEffects()) in isGuardAsWidenableBranch()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp181 static AddrMode DecodeSrcAddrModeI(unsigned Insn) { in DecodeSrcAddrModeI() argument
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI()
183 unsigned As = fieldFromInstruction(Insn, 4, 2); in DecodeSrcAddrModeI()
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII()
189 unsigned As = fieldFromInstruction(Insn, 4, 2); in DecodeSrcAddrModeII()
193 static AddrMode DecodeDstAddrMode(unsigned Insn) { in DecodeDstAddrMode() argument
194 unsigned Rd = fieldFromInstruction(Insn, 0, 4); in DecodeDstAddrMode()
195 unsigned Ad = fieldFromInstruction(Insn, 7, 1); in DecodeDstAddrMode()
234 AddrMode SrcAM = DecodeSrcAddrModeI(Insn); in getInstructionI()
235 AddrMode DstAM = DecodeDstAddrMode(Insn); in getInstructionI()
[all …]
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DPseudoLoweringEmitter.cpp55 CodeGenInstruction &Insn,
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) { in addDagOperandMapping()
106 OpsAdded += Insn.Operands[i].MINumOperands; in addDagOperandMapping()
156 CodeGenInstruction Insn(Operator); in evaluateExpansion() local
158 if (Insn.isCodeGenOnly || Insn.isPseudo) { in evaluateExpansion()
166 if (Insn.Operands.size() != Dag->getNumArgs()) { in evaluateExpansion()
175 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) in evaluateExpansion()
176 NumMIOperands += Insn.Operands[i].MINumOperands; in evaluateExpansion()
180 addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0); in evaluateExpansion()
198 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) { in evaluateExpansion()
[all …]
H A DDecoderEmitter.cpp458 Insn[i] = BIT_UNSET; in insnWithID()
460 Insn[i] = bitFromBits(Bits, i); in insnWithID()
506 const insn_t &Insn) const;
589 insn_t Insn; in Filter() local
1039 if (Insn[StartBit + i] == BIT_UNSET) in fieldFromInsn()
1042 if (Insn[StartBit + i] == BIT_TRUE) in fieldFromInsn()
1103 int64_t Val = Value(Insn[i]); in getIslands()
1416 insn_t Insn; in emitSingletonTableEntry() local
1417 insnWithID(Insn, Opc.EncodingID); in emitSingletonTableEntry()
1552 insn_t Insn; in filterProcessor() local
[all …]
/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DInstructionPrecedenceTracking.h62 bool isPreceededBySpecialInstruction(const Instruction *Insn);
69 virtual bool isSpecialInstruction(const Instruction *Insn) const = 0;
114 bool isDominatedByICFIFromSameBlock(const Instruction *Insn) { in isDominatedByICFIFromSameBlock() argument
115 return isPreceededBySpecialInstruction(Insn); in isDominatedByICFIFromSameBlock()
118 bool isSpecialInstruction(const Instruction *Insn) const override;
137 bool isDominatedByMemoryWriteFromSameBlock(const Instruction *Insn) { in isDominatedByMemoryWriteFromSameBlock() argument
138 return isPreceededBySpecialInstruction(Insn); in isDominatedByMemoryWriteFromSameBlock()
141 bool isSpecialInstruction(const Instruction *Insn) const override;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp352 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
378 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrSImm()
390 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrRdSImm()
403 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrRdRs1UImm()
413 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs2()
414 unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrRdRs2()
423 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs1Rs2()
424 unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrRdRs1Rs2()
437 uint32_t Insn; in getInstruction() local
446 Insn = support::endian::read32le(Bytes.data()); in getInstruction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp127 static DecodeStatus decodeMemoryOpValue(MCInst &Inst, unsigned Insn, in decodeMemoryOpValue() argument
130 unsigned Register = (Insn >> 16) & 0xf; in decodeMemoryOpValue()
135 unsigned Offset = (Insn & 0xffff); in decodeMemoryOpValue()
143 uint64_t &Size, uint64_t &Insn, in readInstruction64() argument
161 Insn = Make_64(Hi, Lo); in readInstruction64()
171 uint64_t Insn, Hi; in getInstruction() local
174 Result = readInstruction64(Bytes, Address, Size, Insn, IsLittleEndian); in getInstruction()
177 uint8_t InstClass = getInstClass(Insn); in getInstruction()
178 uint8_t InstMode = getInstMode(Insn); in getInstruction()
180 getInstSize(Insn) != BPF_DW && in getInstruction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/M68k/Disassembler/
H A DM68kDisassembler.cpp91 static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst, APInt &Insn, in DecodeCCRCRegisterClass() argument
115 auto MakeUp = [&](APInt &Insn, unsigned InstrBits) { in getInstruction() argument
116 unsigned Idx = Insn.getBitWidth() >> 3; in getInstruction()
118 if (RoundUp > Insn.getBitWidth()) in getInstruction()
119 Insn = Insn.zext(RoundUp); in getInstruction()
122 Insn.insertBits(support::endian::read16be(&Bytes[Idx]), Idx * 8, 16); in getInstruction()
125 APInt Insn(16, support::endian::read16be(Bytes.data())); in getInstruction() local
130 Result = decodeInstruction(DecoderTable80, Instr, Insn, Address, this, STI, in getInstruction()
/llvm-project-15.0.7/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/
H A DRuntimeDyldELFMips.cpp215 uint32_t Insn = readBytesUnaligned(TargetPtr, 4); in applyMIPSRelocation() local
233 Insn = (Insn & 0xffff0000) | (Value & 0x0000ffff); in applyMIPSRelocation()
234 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
237 Insn = (Insn & 0xfffc0000) | (Value & 0x0003ffff); in applyMIPSRelocation()
238 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
241 Insn = (Insn & 0xfff80000) | (Value & 0x0007ffff); in applyMIPSRelocation()
242 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
245 Insn = (Insn & 0xffe00000) | (Value & 0x001fffff); in applyMIPSRelocation()
246 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
250 Insn = (Insn & 0xfc000000) | (Value & 0x03ffffff); in applyMIPSRelocation()
[all …]
H A DRuntimeDyldMachOARM.h271 uint32_t Insn = readBytesUnaligned(LocalAddress, 4); in resolveRelocation() local
274 Insn = (Insn & 0x8f00fbf0) | ((Value & 0xf000) >> 12) | in resolveRelocation()
278 Insn = (Insn & 0xfff0f000) | ((Value & 0xf000) << 4) | (Value & 0x0fff); in resolveRelocation()
279 writeBytesUnaligned(Insn, LocalAddress, 4); in resolveRelocation()
/llvm-project-15.0.7/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp1743 InternalInstruction Insn; in getInstruction() local
1745 Insn.bytes = Bytes; in getInstruction()
1748 Insn.mode = fMode; in getInstruction()
1750 if (Bytes.empty() || readPrefixes(&Insn) || readOpcode(&Insn) || in getInstruction()
1751 getInstructionID(&Insn, MII.get()) || Insn.instructionID == 0 || in getInstruction()
1752 readOperands(&Insn)) { in getInstruction()
1757 Insn.operands = x86OperandSets[Insn.spec->operands]; in getInstruction()
1758 Insn.length = Insn.readerCursor - Insn.startLocation; in getInstruction()
1759 Size = Insn.length; in getInstruction()
1766 if (Insn.hasAdSize) in getInstruction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/Disassembler/
H A DLoongArchDisassembler.cpp129 uint32_t Insn; in getInstruction() local
139 Insn = support::endian::read32le(Bytes.data()); in getInstruction()
141 Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); in getInstruction()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp520 uint32_t Insn; in getInstruction() local
523 Insn = support::endian::read16le(Bytes.data()); in getInstruction()
525 if ((Insn >> 14) == 0x3) { in getInstruction()
530 Insn = (Insn << 16) | support::endian::read16le(&Bytes[2]); in getInstruction()
532 if (decodeFPUV3Instruction(MI, Insn, Address, this, STI)) in getInstruction()
536 Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); in getInstruction()
546 Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI); in getInstruction()
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DGVNHoist.cpp647 Instruction *Insn = MU->getMemoryInst(); in hasMemoryUse() local
650 if (BB == OldBB && firstInBB(OldPt, Insn)) in hasMemoryUse()
656 if (firstInBB(Insn, NewPt)) in hasMemoryUse()
812 Instruction *Insn = CHI.I; in checkSafety() local
813 if (!Insn) // No instruction was inserted in this CHI. in checkSafety()
816 if (safeToHoistScalar(BB, Insn->getParent(), NumBBsOnAllPaths)) in checkSafety()
820 if (MemoryUseOrDef *UD = MSSA->getMemoryAccess(Insn)) in checkSafety()
821 if (safeToHoistLdSt(T, Insn, UD, K, NumBBsOnAllPaths)) in checkSafety()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp314 uint64_t &Size, uint32_t &Insn, in readInstruction32() argument
322 Insn = IsLittleEndian in readInstruction32()
335 uint32_t Insn; in getInstruction() local
338 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian); in getInstruction()
346 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI); in getInstruction()
350 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI); in getInstruction()
356 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI); in getInstruction()

123