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Searched refs:IndexOp (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/polly/lib/CodeGen/
H A DIslExprBuilder.cpp243 Value *Base, *IndexOp, *Access; in createAccessAddress() local
288 IndexOp = nullptr; in createAccessAddress()
297 if (!IndexOp) { in createAccessAddress()
298 IndexOp = NextIndex; in createAccessAddress()
304 if (Ty != IndexOp->getType()) in createAccessAddress()
305 IndexOp = Builder.CreateIntCast(IndexOp, Ty, true); in createAccessAddress()
307 IndexOp = createAdd(IndexOp, NextIndex, "polly.access.add." + BaseName); in createAccessAddress()
328 if (Ty != IndexOp->getType()) in createAccessAddress()
329 IndexOp = Builder.CreateSExtOrTrunc(IndexOp, Ty, in createAccessAddress()
334 IndexOp = createMul(IndexOp, DimSize, "polly.access.mul." + BaseName); in createAccessAddress()
[all …]
/llvm-project-15.0.7/mlir/lib/Dialect/Linalg/Transforms/
H A DInterchange.cpp92 for (IndexOp indexOp : in interchangeGenericOp()
93 llvm::make_early_inc_range(genericOp.getBody()->getOps<IndexOp>())) { in interchangeGenericOp()
99 return rewriter.create<IndexOp>(indexOp->getLoc(), dim); in interchangeGenericOp()
H A DElementwiseOpFusion.cpp164 return rewriter.create<IndexOp>(producer.getLoc(), dim); in generateFusedElementwiseOpRegion()
166 for (IndexOp indexOp : in generateFusedElementwiseOpRegion()
167 llvm::make_early_inc_range(producerBlock.getOps<IndexOp>())) { in generateFusedElementwiseOpRegion()
217 if (!isa<IndexOp>(op)) in generateFusedElementwiseOpRegion()
646 for (IndexOp indexOp : in updateExpandedGenericOpRegion()
647 llvm::make_early_inc_range(fusedRegion.front().getOps<IndexOp>())) { in updateExpandedGenericOpRegion()
666 [&](int64_t dim) { return rewriter.create<IndexOp>(loc, dim); }); in updateExpandedGenericOpRegion()
667 Value newIndex = rewriter.create<IndexOp>(loc, expandedDims.front()); in updateExpandedGenericOpRegion()
1301 auto indexOps = llvm::to_vector(block->getOps<linalg::IndexOp>()); in generateCollapsedIndexingRegion()
1315 rewriter.create<linalg::IndexOp>(loc, foldedDims.index()); in generateCollapsedIndexingRegion()
H A DDropUnitDims.cpp151 for (IndexOp indexOp : in replaceUnitDimIndexOps()
152 llvm::make_early_inc_range(genericOp.getBody()->getOps<IndexOp>())) { in replaceUnitDimIndexOps()
162 rewriter.replaceOpWithNewOp<IndexOp>(indexOp, in replaceUnitDimIndexOps()
H A DLoops.cpp190 for (IndexOp indexOp : in replaceIndexOpsByInductionVariables()
191 llvm::make_early_inc_range(loopOp.getLoopBody().getOps<IndexOp>())) in replaceIndexOpsByInductionVariables()
H A DVectorization.cpp273 IndexOp indexOp = dyn_cast<linalg::IndexOp>(op); in vectorizeLinalgIndex()
/llvm-project-15.0.7/mlir/lib/Conversion/TosaToLinalg/
H A DTosaToLinalg.cpp1380 Value batch = rewriter.create<linalg::IndexOp>(loc, 0); in matchAndRewrite()
1381 Value y = rewriter.create<linalg::IndexOp>(loc, 1); in matchAndRewrite()
1382 Value x = rewriter.create<linalg::IndexOp>(loc, 2); in matchAndRewrite()
1383 Value channel = rewriter.create<linalg::IndexOp>(loc, 3); in matchAndRewrite()
1746 rewriter.create<linalg::IndexOp>(nestedLoc, i).getResult(); in matchAndRewrite()
2010 rewriter.create<linalg::IndexOp>(loc, axis)); in matchAndRewrite()
2081 auto index0 = rewriter.create<linalg::IndexOp>(loc, 0); in matchAndRewrite()
2084 auto index2 = rewriter.create<linalg::IndexOp>(loc, 2); in matchAndRewrite()
H A DTosaToLinalgNamed.cpp839 auto y0 = rewriter.create<linalg::IndexOp>(loc, 1); in matchAndRewrite()
840 auto x0 = rewriter.create<linalg::IndexOp>(loc, 2); in matchAndRewrite()
/llvm-project-15.0.7/mlir/lib/Dialect/Linalg/Utils/
H A DUtils.cpp156 linalg::IndexOp>(op) || in hasOnlyScalarElementwiseOp()
1061 for (IndexOp indexOp : linalgOp.getBlock()->getOps<IndexOp>()) { in offsetIndices()
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Linalg/IR/
H A DLinalgStructuredOps.td37 return !this->getBody()->getOps<IndexOp>().empty();
/llvm-project-15.0.7/mlir/lib/Dialect/SparseTensor/Utils/
H A DMerger.cpp844 if (isa<linalg::IndexOp>(def)) in isAdmissableBranchExp()
890 if (auto indexOp = dyn_cast<linalg::IndexOp>(def)) in buildTensorExp()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp222 bool selectVectorAddr(MemSDNode *Parent, SDValue BasePtr, SDValue IndexOp,
2604 SDValue IndexOp, SDValue ScaleOp, in selectVectorAddr() argument
2609 AM.IndexReg = IndexOp; in selectVectorAddr()
5912 SDValue IndexOp = Mgt->getIndex(); in Select() local
5914 MVT IndexVT = IndexOp.getSimpleValueType(); in Select()
5982 if (!selectVectorAddr(Mgt, Mgt->getBasePtr(), IndexOp, Mgt->getScale(), in Select()
6010 SDValue IndexOp = Sc->getIndex(); in Select() local
6011 MVT IndexVT = IndexOp.getSimpleValueType(); in Select()
6055 if (!selectVectorAddr(Sc, Sc->getBasePtr(), IndexOp, Sc->getScale(), in Select()
/llvm-project-15.0.7/mlir/python/mlir/dialects/linalg/opdsl/lang/
H A Demitter.py292 return linalg.IndexOp(dim_attr).result
/llvm-project-15.0.7/bolt/lib/Target/X86/
H A DX86MCPlusBuilder.cpp1835 MCOperand &IndexOp = in shortenInstruction() local
1837 if (IndexOp.getReg() == X86::EIZ || IndexOp.getReg() == X86::RIZ) in shortenInstruction()
1838 IndexOp = MCOperand::createReg(X86::NoRegister); in shortenInstruction()
/llvm-project-15.0.7/mlir/lib/Dialect/Linalg/IR/
H A DLinalgOps.cpp409 return builder.create<IndexOp>(builder.getUnknownLoc(), dim); in index()
1524 LogicalResult IndexOp::verify() { in verify()
/llvm-project-15.0.7/mlir/lib/Dialect/SparseTensor/Transforms/
H A DSparsification.cpp936 if (auto indexOp = dyn_cast<linalg::IndexOp>(def)) in relinkBranch()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuiltin.cpp7270 Value *ExtOp, Value *IndexOp, in packTBLDVectorList() argument
7302 TblOps.push_back(IndexOp); in packTBLDVectorList()