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Searched refs:Fixups (Results 1 – 25 of 78) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCCodeEmitter.cpp114 return getPCRelEncoding(MI, OpNum, Fixups, in getPC16DBLEncoding()
120 return getPCRelEncoding(MI, OpNum, Fixups, in getPC32DBLEncoding()
126 return getPCRelEncoding(MI, OpNum, Fixups, in getPC16DBLTLSEncoding()
132 return getPCRelEncoding(MI, OpNum, Fixups, in getPC32DBLTLSEncoding()
138 return getPCRelEncoding(MI, OpNum, Fixups, in getPC12DBLBPPEncoding()
144 return getPCRelEncoding(MI, OpNum, Fixups, in getPC16DBLBPPEncoding()
150 return getPCRelEncoding(MI, OpNum, Fixups, in getPC24DBLBPPEncoding()
173 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue() argument
184 SmallVectorImpl<MCFixup> &Fixups, in getDispOpValue() argument
205 SmallVectorImpl<MCFixup> &Fixups, in getBDAddr12Encoding() argument
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.h51 SmallVectorImpl<MCFixup> &Fixups,
57 SmallVectorImpl<MCFixup> &Fixups,
64 SmallVectorImpl<MCFixup> &Fixups,
77 SmallVectorImpl<MCFixup> &Fixups,
81 SmallVectorImpl<MCFixup> &Fixups,
85 SmallVectorImpl<MCFixup> &Fixups,
91 SmallVectorImpl<MCFixup> &Fixups,
181 SmallVectorImpl<MCFixup> &Fixups,
185 SmallVectorImpl<MCFixup> &Fixups,
190 SmallVectorImpl<MCFixup> &Fixups,
[all …]
H A DMipsMCCodeEmitter.cpp152 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction() argument
180 unsigned long N = Fixups.size(); in encodeInstruction()
206 if (Fixups.size() > N) in encodeInstruction()
207 Fixups.pop_back(); in encodeInstruction()
336 Fixups.push_back(MCFixup::create(0, Expr, in getBranchTarget7OpValueMM()
357 Fixups.push_back(MCFixup::create(0, Expr, in getBranchTargetOpValueMMPC10()
378 Fixups.push_back(MCFixup::create(0, Expr, in getBranchTargetOpValueMM()
487 Mips::Fixups FixupKind = in getJumpOffset16OpValue()
508 Fixups.push_back(MCFixup::create(0, Expr, in getJumpTargetOpValue()
525 Fixups.push_back(MCFixup::create(0, Expr, in getJumpTargetOpValueMM()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp43 SmallVectorImpl<MCFixup> &Fixups, in getDirectBrEncoding() argument
48 return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
53 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getDirectBrEncoding()
67 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getCondBrEncoding()
80 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getAbsDirectBrEncoding()
93 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getAbsCondBrEncoding()
127 return getMachineOpValue(MI, MO, Fixups, STI); in getImm34Encoding()
138 return getImm34Encoding(MI, OpNo, Fixups, STI, in getImm34EncodingNoPCRel()
146 return getImm34Encoding(MI, OpNo, Fixups, STI, in getImm34EncodingPCRel()
271 Fixups.push_back( in getMemRI34PCRelEncoding()
[all …]
H A DPPCMCCodeEmitter.h39 SmallVectorImpl<MCFixup> &Fixups,
42 SmallVectorImpl<MCFixup> &Fixups,
51 SmallVectorImpl<MCFixup> &Fixups,
54 SmallVectorImpl<MCFixup> &Fixups,
64 SmallVectorImpl<MCFixup> &Fixups,
67 SmallVectorImpl<MCFixup> &Fixups,
79 SmallVectorImpl<MCFixup> &Fixups,
82 SmallVectorImpl<MCFixup> &Fixups,
91 SmallVectorImpl<MCFixup> &Fixups,
106 SmallVectorImpl<MCFixup> &Fixups,
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp56 SmallVectorImpl<MCFixup> &Fixups,
62 SmallVectorImpl<MCFixup> &Fixups,
70 SmallVectorImpl<MCFixup> &Fixups,
76 SmallVectorImpl<MCFixup> &Fixups,
82 SmallVectorImpl<MCFixup> &Fixups,
165 SmallVectorImpl<MCFixup> &Fixups,
168 SmallVectorImpl<MCFixup> &Fixups,
175 SmallVectorImpl<MCFixup> &Fixups,
355 Fixups.push_back(MCFixup::create( in getMoveWideImmOpValue()
620 Fixups.push_back( in encodeInstruction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.h36 SmallVectorImpl<MCFixup> &Fixups,
46 SmallVectorImpl<MCFixup> &Fixups,
51 SmallVectorImpl<MCFixup> &Fixups, in getImmOpValue() argument
73 SmallVectorImpl<MCFixup> &Fixups,
81 SmallVectorImpl<MCFixup> &Fixups,
98 template <llvm::CSKY::Fixups FIXUP>
117 template <llvm::CSKY::Fixups FIXUP>
132 template <llvm::CSKY::Fixups FIXUP>
176 SmallVectorImpl<MCFixup> &Fixups,
179 SmallVectorImpl<MCFixup> &Fixups,
[all …]
H A DCSKYMCCodeEmitter.cpp82 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in expandJBTF()
91 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in expandJBTF()
92 Fixups[Fixups.size() - 1].setOffset(2); in expandJBTF()
107 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in expandNEG()
114 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in expandNEG()
129 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in expandRSUBI()
136 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in expandRSUBI()
154 expandJBTF(MI, OS, Fixups, STI); in encodeInstruction()
159 expandNEG(MI, OS, Fixups, STI); in encodeInstruction()
164 expandRSUBI(MI, OS, Fixups, STI); in encodeInstruction()
[all …]
H A DCSKYAsmBackend.cpp35 {CSKY::Fixups::fixup_csky_pcrel_imm16_scale2, in getFixupKindInfo()
37 {CSKY::Fixups::fixup_csky_pcrel_uimm16_scale4, in getFixupKindInfo()
41 {CSKY::Fixups::fixup_csky_pcrel_uimm8_scale4, in getFixupKindInfo()
45 {CSKY::Fixups::fixup_csky_pcrel_imm26_scale2, in getFixupKindInfo()
47 {CSKY::Fixups::fixup_csky_pcrel_imm18_scale2, in getFixupKindInfo()
50 {CSKY::Fixups::fixup_csky_got_imm18_scale4, in getFixupKindInfo()
53 {CSKY::Fixups::fixup_csky_gotpc, in getFixupKindInfo()
56 {CSKY::Fixups::fixup_csky_plt_imm18_scale4, in getFixupKindInfo()
58 {CSKY::Fixups::fixup_csky_pcrel_imm10_scale2, in getFixupKindInfo()
60 {CSKY::Fixups::fixup_csky_pcrel_uimm7_scale4, in getFixupKindInfo()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp353 SmallVectorImpl<MCFixup> &Fixups,
357 SmallVectorImpl<MCFixup> &Fixups,
360 SmallVectorImpl<MCFixup> &Fixups,
454 template <bool isNeg, ARM::Fixups fixup>
664 Fixups, STI); in getThumbBLTargetOpValue()
677 Fixups, STI); in getThumbBLXTargetOpValue()
689 Fixups, STI); in getThumbBRTargetOpValue()
701 Fixups, STI); in getThumbBCCTargetOpValue()
829 Fixups, STI); in getAdrLabelOpValue()
870 Fixups, STI); in getT2AdrLabelOpValue()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCCodeEmitter.cpp122 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue() argument
173 Fixups.push_back(MCFixup::create(0, Expr, Kind)); in getSImm13OpValue()
200 Fixups.push_back(MCFixup::create(0, Expr, Kind)); in getCallTargetOpValue()
206 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValue() argument
210 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchTargetOpValue()
212 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getBranchTargetOpValue()
223 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchPredTargetOpValue()
225 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getBranchPredTargetOpValue()
236 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchOnRegTargetOpValue()
238 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getBranchOnRegTargetOpValue()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/VE/MCTargetDesc/
H A DVEMCCodeEmitter.cpp52 SmallVectorImpl<MCFixup> &Fixups,
58 SmallVectorImpl<MCFixup> &Fixups,
64 SmallVectorImpl<MCFixup> &Fixups,
68 SmallVectorImpl<MCFixup> &Fixups,
71 SmallVectorImpl<MCFixup> &Fixups,
74 SmallVectorImpl<MCFixup> &Fixups,
83 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction()
103 Fixups.push_back(MCFixup::create(0, Expr, Kind)); in getMachineOpValue()
121 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchTargetOpValue()
123 Fixups.push_back( in getBranchTargetOpValue()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCCodeEmitter.cpp46 SmallVectorImpl<MCFixup> &Fixups,
54 SmallVectorImpl<MCFixup> &Fixups,
58 SmallVectorImpl<MCFixup> &Fixups,
62 SmallVectorImpl<MCFixup> &Fixups,
66 SmallVectorImpl<MCFixup> &Fixups,
70 SmallVectorImpl<MCFixup> &Fixups,
78 SmallVectorImpl<MCFixup> &Fixups,
114 Fixups.push_back(MCFixup::create(Offset, MO.getExpr(), in getMachineOpValue()
134 MSP430::Fixups FixupKind; in getMemOpValue()
146 Fixups.push_back(MCFixup::create(Offset, MO2.getExpr(), in getMemOpValue()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.h50 template <AVR::Fixups Fixup>
52 SmallVectorImpl<MCFixup> &Fixups,
57 SmallVectorImpl<MCFixup> &Fixups,
62 SmallVectorImpl<MCFixup> &Fixups,
67 SmallVectorImpl<MCFixup> &Fixups,
72 template <AVR::Fixups Fixup, unsigned Offset>
74 SmallVectorImpl<MCFixup> &Fixups,
79 SmallVectorImpl<MCFixup> &Fixups,
84 SmallVectorImpl<MCFixup> &Fixups,
95 SmallVectorImpl<MCFixup> &Fixups,
[all …]
H A DAVRMCCodeEmitter.cpp91 template <AVR::Fixups Fixup>
99 Fixups.push_back( in encodeRelCondBrTarget()
138 SmallVectorImpl<MCFixup> &Fixups, in encodeMemri() argument
164 Fixups.push_back(MCFixup::create(0, OffsetOp.getExpr(), in encodeMemri()
183 template <AVR::Fixups Fixup, unsigned Offset>
185 SmallVectorImpl<MCFixup> &Fixups, in encodeImm() argument
195 return getExprOpValue(MO.getExpr(), Fixups, STI); in encodeImm()
199 Fixups.push_back( in encodeImm()
246 Fixups.push_back(MCFixup::create(0, AVRExpr, FixupKind)); in getExprOpValue()
269 return getExprOpValue(MO.getExpr(), Fixups, STI); in getMachineOpValue()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCCodeEmitter.cpp61 SmallVectorImpl<MCFixup> &Fixups,
85 SmallVectorImpl<MCFixup> &Fixups,
130 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in expandFunctionCall()
140 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in expandFunctionCall()
163 Fixups.push_back(MCFixup::create( in expandAddTPRel()
169 Fixups.push_back(MCFixup::create( in expandAddTPRel()
196 expandFunctionCall(MI, OS, Fixups, STI); in encodeInstruction()
202 expandAddTPRel(MI, OS, Fixups, STI); in encodeInstruction()
252 return getImmOpValue(MI, OpNo, Fixups, STI); in getImmOpValueAsr1()
363 Fixups.push_back( in getImmOpValue()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp58 SmallVectorImpl<MCFixup> &Fixups,
62 SmallVectorImpl<MCFixup> &Fixups,
66 SmallVectorImpl<MCFixup> &Fixups,
70 SmallVectorImpl<MCFixup> &Fixups,
78 SmallVectorImpl<MCFixup> &Fixups,
90 static Lanai::Fixups FixupKind(const MCExpr *Expr) { in FixupKind()
104 return Lanai::Fixups(0); in FixupKind()
129 Fixups.push_back( in getMachineOpValue()
212 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo); in getRiMemoryOpValue()
283 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo); in getSplsOpValue()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchMCCodeEmitter.cpp40 SmallVectorImpl<MCFixup> &Fixups,
46 SmallVectorImpl<MCFixup> &Fixups,
52 SmallVectorImpl<MCFixup> &Fixups,
60 SmallVectorImpl<MCFixup> &Fixups,
69 SmallVectorImpl<MCFixup> &Fixups,
76 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue() argument
90 SmallVectorImpl<MCFixup> &Fixups, in getImmOpValueSub1() argument
97 SmallVectorImpl<MCFixup> &Fixups, in getImmOpValueAsr2() argument
105 const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction() argument
115 uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction()
/llvm-project-15.0.7/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp48 SmallVectorImpl<MCFixup> &Fixups,
54 SmallVectorImpl<MCFixup> &Fixups,
58 SmallVectorImpl<MCFixup> &Fixups,
62 SmallVectorImpl<MCFixup> &Fixups,
80 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue() argument
95 Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_4)); in getMachineOpValue()
97 Fixups.push_back(MCFixup::create(0, Expr, FK_SecRel_8)); in getMachineOpValue()
100 Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_2)); in getMachineOpValue()
111 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction() argument
118 uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.h37 void getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
42 APInt &Op, SmallVectorImpl<MCFixup> &Fixups,
46 SmallVectorImpl<MCFixup> &Fixups,
50 SmallVectorImpl<MCFixup> &Fixups,
54 SmallVectorImpl<MCFixup> &Fixups,
59 SmallVectorImpl<MCFixup> &Fixups,
63 SmallVectorImpl<MCFixup> &Fixups,
H A DSIMCCodeEmitter.cpp49 SmallVectorImpl<MCFixup> &Fixups,
54 SmallVectorImpl<MCFixup> &Fixups,
60 SmallVectorImpl<MCFixup> &Fixups,
64 SmallVectorImpl<MCFixup> &Fixups,
68 SmallVectorImpl<MCFixup> &Fixups,
72 SmallVectorImpl<MCFixup> &Fixups,
76 SmallVectorImpl<MCFixup> &Fixups,
83 SmallVectorImpl<MCFixup> &Fixups,
322 getBinaryCodeForInstr(MI, Fixups, Encoding, Scratch, STI); in encodeInstruction()
423 getMachineOpValue(MI, MO, Op, Fixups, STI); in getSOPPBrEncoding()
[all …]
H A DR600MCCodeEmitter.cpp43 SmallVectorImpl<MCFixup> &Fixups,
48 SmallVectorImpl<MCFixup> &Fixups,
59 SmallVectorImpl<MCFixup> &Fixups,
88 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction() argument
98 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction()
122 uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction()
132 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction()
158 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue() argument
174 Fixups.push_back(MCFixup::create(offset, MO.getExpr(), FK_SecRel_4, MI.getLoc())); in getMachineOpValue()
/llvm-project-15.0.7/llvm/lib/Target/M68k/MCTargetDesc/
H A DM68kMCCodeEmitter.cpp49 SmallVectorImpl<MCFixup> &Fixups,
54 APInt &Value, SmallVectorImpl<MCFixup> &Fixups,
59 APInt &Value, SmallVectorImpl<MCFixup> &Fixups,
69 SmallVectorImpl<MCFixup> &Fixups,
133 SmallVectorImpl<MCFixup> &Fixups, in encodeRelocImm() argument
151 Fixups.push_back(MCFixup::create(InsertByte, Expr, in encodeRelocImm()
160 SmallVectorImpl<MCFixup> &Fixups, in encodePCRelImm() argument
187 Fixups.push_back(MCFixup::create(InsertByte, Expr, in encodePCRelImm()
195 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue() argument
221 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction() argument
[all …]
/llvm-project-15.0.7/llvm/test/TableGen/
H A DVarLenEncoder.td70 // CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI);
73 // CHECK: getMachineOpValue(MI, MI.getOperand(2), /*Pos=*/16, Scratch, Fixups, STI);
76 // CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/32, Scratch, Fixups, STI);
79 // CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/36, Scratch, Fixups, STI);
82 // CHECK: myCustomEncoder(MI, /*OpIdx=*/0, /*Pos=*/39, Scratch, Fixups, STI);
88 // CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI);
91 // CHECK: getMachineOpValue(MI, MI.getOperand(2), /*Pos=*/16, Scratch, Fixups, STI);
94 // CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/48, Scratch, Fixups, STI);
97 // CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/52, Scratch, Fixups, STI);
100 // CHECK: myCustomEncoder(MI, /*OpIdx=*/0, /*Pos=*/55, Scratch, Fixups, STI);
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.h53 SmallVectorImpl<MCFixup> &Fixups,
57 SmallVectorImpl<MCFixup> &Fixups,
64 SmallVectorImpl<MCFixup> &Fixups,
69 SmallVectorImpl<MCFixup> &Fixups,
75 const MCExpr *ME, SmallVectorImpl<MCFixup> &Fixups,
78 Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,

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