Lines Matching refs:Fixups
152 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction() argument
180 unsigned long N = Fixups.size(); in encodeInstruction()
181 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in encodeInstruction()
206 if (Fixups.size() > N) in encodeInstruction()
207 Fixups.pop_back(); in encodeInstruction()
210 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in encodeInstruction()
215 unsigned RegPair = getMovePRegPairOpValue(MI, 0, Fixups, STI); in encodeInstruction()
235 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValue() argument
247 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTargetOpValue()
257 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValue1SImm16() argument
269 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTargetOpValue1SImm16()
279 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValueMMR6() argument
292 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTargetOpValueMMR6()
302 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValueLsl2MMR6() argument
315 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTargetOpValueLsl2MMR6()
325 SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget7OpValueMM() argument
336 Fixups.push_back(MCFixup::create(0, Expr, in getBranchTarget7OpValueMM()
346 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValueMMPC10() argument
357 Fixups.push_back(MCFixup::create(0, Expr, in getBranchTargetOpValueMMPC10()
367 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValueMM() argument
378 Fixups.push_back(MCFixup::create(0, Expr, in getBranchTargetOpValueMM()
389 SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget21OpValue() argument
401 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTarget21OpValue()
411 SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget21OpValueMM() argument
423 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTarget21OpValueMM()
433 SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget26OpValue() argument
445 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTarget26OpValue()
454 const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget26OpValueMM() argument
467 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTarget26OpValueMM()
477 SmallVectorImpl<MCFixup> &Fixups, in getJumpOffset16OpValue() argument
487 Mips::Fixups FixupKind = in getJumpOffset16OpValue()
489 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind))); in getJumpOffset16OpValue()
498 SmallVectorImpl<MCFixup> &Fixups, in getJumpTargetOpValue() argument
508 Fixups.push_back(MCFixup::create(0, Expr, in getJumpTargetOpValue()
515 SmallVectorImpl<MCFixup> &Fixups, in getJumpTargetOpValueMM() argument
525 Fixups.push_back(MCFixup::create(0, Expr, in getJumpTargetOpValueMM()
532 SmallVectorImpl<MCFixup> &Fixups, in getUImm5Lsl2Encoding() argument
537 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); in getUImm5Lsl2Encoding()
550 SmallVectorImpl<MCFixup> &Fixups, in getSImm3Lsa2Value() argument
563 SmallVectorImpl<MCFixup> &Fixups, in getUImm6Lsl2Encoding() argument
576 SmallVectorImpl<MCFixup> &Fixups, in getSImm9AddiuspValue() argument
588 getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, in getExprOpValue() argument
602 getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI); in getExprOpValue()
603 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI); in getExprOpValue()
610 Mips::Fixups FixupKind = Mips::Fixups(0); in getExprOpValue()
619 return getExprOpValue(MipsExpr->getSubExpr(), Fixups, STI); in getExprOpValue()
720 Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind))); in getExprOpValue()
733 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue() argument
746 return getExprOpValue(MO.getExpr(),Fixups, STI); in getMachineOpValue()
753 SmallVectorImpl<MCFixup> &Fixups, in getMemEncoding() argument
757 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) in getMemEncoding()
759 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncoding()
769 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm4() argument
774 Fixups, STI) << 4; in getMemEncodingMMImm4()
776 Fixups, STI); in getMemEncodingMMImm4()
783 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm4Lsl1() argument
788 Fixups, STI) << 4; in getMemEncodingMMImm4Lsl1()
790 Fixups, STI) >> 1; in getMemEncodingMMImm4Lsl1()
797 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm4Lsl2() argument
802 Fixups, STI) << 4; in getMemEncodingMMImm4Lsl2()
804 Fixups, STI) >> 2; in getMemEncodingMMImm4Lsl2()
811 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMSPImm5Lsl2() argument
819 Fixups, STI) >> 2; in getMemEncodingMMSPImm5Lsl2()
826 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMGPImm7Lsl2() argument
834 Fixups, STI) >> 2; in getMemEncodingMMGPImm7Lsl2()
841 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm9() argument
845 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, in getMemEncodingMMImm9()
848 getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI); in getMemEncodingMMImm9()
855 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm11() argument
859 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, in getMemEncodingMMImm11()
861 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm11()
868 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm12() argument
883 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) in getMemEncodingMMImm12()
885 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm12()
892 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm16() argument
896 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, in getMemEncodingMMImm16()
898 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm16()
905 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm4sp() argument
924 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm4sp()
933 SmallVectorImpl<MCFixup> &Fixups, in getSizeInsEncoding() argument
937 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI); in getSizeInsEncoding()
938 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); in getSizeInsEncoding()
946 SmallVectorImpl<MCFixup> &Fixups, in getUImmWithOffsetEncoding() argument
949 unsigned Value = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); in getUImmWithOffsetEncoding()
956 SmallVectorImpl<MCFixup> &Fixups, in getSimm19Lsl2Encoding() argument
961 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); in getSimm19Lsl2Encoding()
970 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC19_S2 in getSimm19Lsl2Encoding()
972 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind))); in getSimm19Lsl2Encoding()
978 SmallVectorImpl<MCFixup> &Fixups, in getSimm18Lsl3Encoding() argument
983 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); in getSimm18Lsl3Encoding()
992 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC18_S3 in getSimm18Lsl3Encoding()
994 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind))); in getSimm18Lsl3Encoding()
1000 SmallVectorImpl<MCFixup> &Fixups, in getUImm3Mod8Encoding() argument
1009 SmallVectorImpl<MCFixup> &Fixups, in getUImm4AndValue() argument
1037 SmallVectorImpl<MCFixup> &Fixups, in getRegisterListOpValue() argument
1057 SmallVectorImpl<MCFixup> &Fixups, in getRegisterListOpValue16() argument
1064 SmallVectorImpl<MCFixup> &Fixups, in getMovePRegPairOpValue() argument
1098 SmallVectorImpl<MCFixup> &Fixups, in getMovePRegSingleOpValue() argument
1121 SmallVectorImpl<MCFixup> &Fixups, in getSimm23Lsl2Encoding() argument