Lines Matching refs:Fixups
43 SmallVectorImpl<MCFixup> &Fixups, in getDirectBrEncoding() argument
48 return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
53 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getDirectBrEncoding()
61 SmallVectorImpl<MCFixup> &Fixups, in getCondBrEncoding() argument
64 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
67 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getCondBrEncoding()
74 SmallVectorImpl<MCFixup> &Fixups, in getAbsDirectBrEncoding() argument
77 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
80 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getAbsDirectBrEncoding()
87 SmallVectorImpl<MCFixup> &Fixups, in getAbsCondBrEncoding() argument
90 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
93 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getAbsCondBrEncoding()
100 SmallVectorImpl<MCFixup> &Fixups, in getVSRpEvenEncoding() argument
103 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) in getVSRpEvenEncoding()
109 SmallVectorImpl<MCFixup> &Fixups, in getImm16Encoding() argument
112 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
115 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), in getImm16Encoding()
121 SmallVectorImpl<MCFixup> &Fixups, in getImm34Encoding() argument
127 return getMachineOpValue(MI, MO, Fixups, STI); in getImm34Encoding()
130 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup)); in getImm34Encoding()
136 SmallVectorImpl<MCFixup> &Fixups, in getImm34EncodingNoPCRel() argument
138 return getImm34Encoding(MI, OpNo, Fixups, STI, in getImm34EncodingNoPCRel()
144 SmallVectorImpl<MCFixup> &Fixups, in getImm34EncodingPCRel() argument
146 return getImm34Encoding(MI, OpNo, Fixups, STI, in getImm34EncodingPCRel()
151 SmallVectorImpl<MCFixup> &Fixups, in getMemRIEncoding() argument
156 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; in getMemRIEncoding()
160 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; in getMemRIEncoding()
163 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), in getMemRIEncoding()
169 SmallVectorImpl<MCFixup> &Fixups, in getMemRIXEncoding() argument
174 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; in getMemRIXEncoding()
178 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits; in getMemRIXEncoding()
181 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), in getMemRIXEncoding()
187 SmallVectorImpl<MCFixup> &Fixups, in getMemRIX16Encoding() argument
192 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12; in getMemRIX16Encoding()
198 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits; in getMemRIX16Encoding()
202 Fixups.push_back(MCFixup::create(IsLittleEndian ? 0 : 2, MO.getExpr(), in getMemRIX16Encoding()
209 SmallVectorImpl<MCFixup> &Fixups, in getMemRIHashEncoding() argument
220 unsigned RegBits = getMachineOpValue(MI, RegMO, Fixups, STI) << 6; in getMemRIHashEncoding()
227 SmallVectorImpl<MCFixup> &Fixups, in getMemRI34PCRelEncoding() argument
241 getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34; in getMemRI34PCRelEncoding()
248 return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits; in getMemRI34PCRelEncoding()
271 Fixups.push_back( in getMemRI34PCRelEncoding()
305 Fixups.push_back( in getMemRI34PCRelEncoding()
317 SmallVectorImpl<MCFixup> &Fixups, in getMemRI34Encoding() argument
322 uint64_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) in getMemRI34Encoding()
325 return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits; in getMemRI34Encoding()
329 SmallVectorImpl<MCFixup> &Fixups, in getSPE8DisEncoding() argument
335 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; in getSPE8DisEncoding()
339 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3; in getSPE8DisEncoding()
344 SmallVectorImpl<MCFixup> &Fixups, in getSPE4DisEncoding() argument
350 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; in getSPE4DisEncoding()
354 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2; in getSPE4DisEncoding()
359 SmallVectorImpl<MCFixup> &Fixups, in getSPE2DisEncoding() argument
365 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; in getSPE2DisEncoding()
369 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1; in getSPE2DisEncoding()
374 SmallVectorImpl<MCFixup> &Fixups, in getTLSRegEncoding() argument
377 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); in getTLSRegEncoding()
386 Fixups.push_back(MCFixup::create(IsPCRel ? 1 : 0, Expr, in getTLSRegEncoding()
394 SmallVectorImpl<MCFixup> &Fixups, in getTLSCallEncoding() argument
400 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getTLSCallEncoding()
402 return getDirectBrEncoding(MI, OpNo, Fixups, STI); in getTLSCallEncoding()
407 SmallVectorImpl<MCFixup> &Fixups, in get_crbitm_encoding() argument
432 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue() argument
453 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction() argument
455 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction()