| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 95 DAG_FUNCTION(sin, 1, 1, experimental_constrained_sin, FSIN)
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 915 FSIN, enumerator
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| H A D | BasicTTIImpl.h | 1688 ISD = ISD::FSIN; in getTypeBasedIntrinsicInstrCost()
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| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | combine-foldable-fneg.mir | 374 ; CHECK-NEXT: [[FSIN:%[0-9]+]]:_(s32) = G_FSIN [[FNEG]]
375 ; CHECK-NEXT: $vgpr0 = COPY [[FSIN]](s32)
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 94 setOperationAction({ISD::FCOS, ISD::FSIN}, MVT::f32, Custom); in R600TargetLowering()
407 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
699 case ISD::FSIN: in LowerTrig()
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| H A D | AMDGPUISelLowering.cpp | 401 ISD::FSQRT, ISD::FSIN, ISD::FSUB, ISD::FNEG, in AMDGPUTargetLowering()
507 case ISD::FSIN: in fnegFoldsIntoOp()
3848 case ISD::FSIN: in performFNegCombine()
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| H A D | SIISelLowering.cpp | 452 setOperationAction({ISD::FSIN, ISD::FCOS, ISD::FDIV}, MVT::f32, Custom); in SITargetLowering()
493 {ISD::FP_ROUND, ISD::FCOS, ISD::FSIN, ISD::FROUND, ISD::FPTRUNC_ROUND}, in SITargetLowering()
4658 case ISD::FSIN: in LowerOperation()
9284 case ISD::FSIN: in LowerTrig()
10057 case ISD::FSIN: in isCanonicalized()
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| H A D | AMDGPUISelDAGToDAG.cpp | 154 case ISD::FSIN: in fp16SrcZerosHighBits()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 197 case ISD::FSIN: return "fsin"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 123 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
1263 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
2271 case ISD::FSIN: in PromoteFloatResult()
2636 case ISD::FSIN: in SoftPromoteHalfResult()
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| H A D | LegalizeDAG.cpp | 2236 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2237 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3200 case ISD::FSIN: in ExpandNode()
4020 case ISD::FSIN: in ConvertNodeToLibcall()
4843 case ISD::FSIN: in PromoteNode()
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| H A D | LegalizeVectorOps.cpp | 368 case ISD::FSIN: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 103 case ISD::FSIN: in ScalarizeVectorResult()
1040 case ISD::FSIN: in SplitVectorResult()
3846 case ISD::FSIN: in WidenVectorResult()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 929 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
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| H A D | X86InstrFPStack.td | 753 def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>;
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1726 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1731 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1736 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 116 ISD::NodeType FPOpToExpand[] = {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in CSKYTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1590 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1635 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 382 setOperationAction(ISD::FSIN , MVT::f64, Expand); in PPCTargetLowering()
387 setOperationAction(ISD::FSIN , MVT::f32, Expand); in PPCTargetLowering()
396 setOperationAction(ISD::FSIN , MVT::f64, Custom); in PPCTargetLowering()
402 setOperationAction(ISD::FSIN , MVT::f32, Custom); in PPCTargetLowering()
839 setOperationAction(ISD::FSIN, VT, Expand); in PPCTargetLowering()
1166 setOperationAction(ISD::FSIN, MVT::f128, Expand); in PPCTargetLowering()
11137 case ISD::FSIN: return lowerSin(Op, DAG); in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 419 setOperationAction(ISD::FSIN, MVT::f32, Expand); in MipsTargetLowering()
420 setOperationAction(ISD::FSIN, MVT::f64, Expand); in MipsTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 124 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 365 setOperationAction(ISD::FSIN, VT, Expand); in addMVEVectorTypes()
874 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); in ARMTargetLowering()
895 setOperationAction(ISD::FSIN, MVT::v4f32, Expand); in ARMTargetLowering()
911 setOperationAction(ISD::FSIN, MVT::v2f32, Expand); in ARMTargetLowering()
1044 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1435 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1436 setOperationAction(ISD::FSIN, MVT::f32, Expand); in ARMTargetLowering()
1519 setOperationAction(ISD::FSIN, MVT::f16, Promote); in ARMTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 247 setOperationAction(ISD::FSIN, VT, Expand); in initSPUActions()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 490 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 441 setOperationAction(ISD::FSIN, MVT::f128, Expand); in AArch64TargetLowering()
577 setOperationAction(ISD::FSIN, MVT::f32, Expand); in AArch64TargetLowering()
578 setOperationAction(ISD::FSIN, MVT::f64, Expand); in AArch64TargetLowering()
591 ISD::FCOS, ISD::FSIN, ISD::FSINCOS, in AArch64TargetLowering()
1328 setOperationAction(ISD::FSIN, VT, Expand); in AArch64TargetLowering()
1464 setOperationAction(ISD::FSIN, VT, Expand); in addTypeForNEON()
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