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Searched refs:FRINT (Results 1 – 25 of 49) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-frint.mir32 ; NOFP16: $s0 = COPY [[FRINT]](s32)
38 ; FP16: $s0 = COPY [[FRINT]](s32)
59 ; NOFP16: $d0 = COPY [[FRINT]](s64)
65 ; FP16: $d0 = COPY [[FRINT]](s64)
86 ; NOFP16: $q0 = COPY [[FRINT]](<4 x s32>)
92 ; FP16: $q0 = COPY [[FRINT]](<4 x s32>)
113 ; NOFP16: $q0 = COPY [[FRINT]](<2 x s64>)
119 ; FP16: $q0 = COPY [[FRINT]](<2 x s64>)
159 ; FP16: $d0 = COPY [[FRINT]](<4 x s16>)
211 ; FP16: $q0 = COPY [[FRINT]](<8 x s16>)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-frint.mir17 ; SI-NEXT: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT]]
27 ; CI-NEXT: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT]]
48 ; SI-NEXT: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[COPY]]
49 ; SI-NEXT: $vgpr0 = COPY [[FRINT]](s32)
54 ; CI-NEXT: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[COPY]]
55 ; CI-NEXT: $vgpr0 = COPY [[FRINT]](s32)
87 ; CI-NEXT: [[FRINT:%[0-9]+]]:_(s64) = G_FRINT [[COPY]]
88 ; CI-NEXT: $vgpr0_vgpr1 = COPY [[FRINT]](s64)
158 ; SI-NEXT: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[UV]]
167 ; CI-NEXT: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[UV]]
[all …]
H A Dregbankselect-frint.mir17 ; CHECK-NEXT: [[FRINT:%[0-9]+]]:vgpr(s32) = G_FRINT [[COPY1]]
33 ; CHECK-NEXT: [[FRINT:%[0-9]+]]:vgpr(s32) = G_FRINT [[COPY]]
H A Dinst-select-frint.s16.mir19 ; GCN-NEXT: [[FRINT:%[0-9]+]]:sreg_32(s16) = G_FRINT [[TRUNC]]
20 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FRINT]](s16)
H A Dcombine-foldable-fneg.mir298 ; CHECK-NEXT: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[FNEG]]
299 ; CHECK-NEXT: $vgpr0 = COPY [[FRINT]](s32)
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def92 DAG_FUNCTION(rint, 1, 1, experimental_constrained_rint, FRINT)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h926 FRINT, enumerator
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedNeoverseN2.td800 def : InstRW<[N2Write_3cyc_1V0], (instregex "^FRINT[AIMNPXZ][HSD]r$",
801 "^FRINT(32|64)[XZ][SD]r$")>;
1099 (instregex "^FRINT[AIMNPXZ]v2f(32|64)$",
1100 "^FRINT[32|64)[XZ]v2f(32|64)$")>;
1104 (instregex "^FRINT[AIMNPXZ]v4f(16|32)$",
1105 "^FRINT(32|64)[XZ]v4f32$")>;
1109 def : InstRW<[N2Write_6cyc_4V0], (instregex "^FRINT[AIMNPXZ]v8f16$")>;
2012 def : InstRW<[N2Write_6cyc_4V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H$")>;
2015 def : InstRW<[N2Write_4cyc_2V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S$")>;
2018 def : InstRW<[N2Write_3cyc_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D$")>;
H A DAArch64SchedAmpere1.td888 def : InstRW<[Ampere1Write_4cyc_1XY], (instregex "^FRINT[AIMNPXZ]v.[if]16")>;
917 def : InstRW<[Ampere1Write_6cyc_1XY], (instregex "^FRINT[AIMNPXZ]v.[if](32|64)")>;
918 def : InstRW<[Ampere1Write_6cyc_1XY], (instregex "^FRINT(32|64)")>;
H A DAArch64SchedA57.td512 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
514 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
586 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
H A DAArch64SchedTSV110.td484 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT.+r")>;
674 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedFalkorDetails.td592 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)v2f32$")>;
617 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)$")>;
1123 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(S|D)r$")>;
H A DAArch64SchedExynosM3.td546 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>;
661 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedExynosM4.td657 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT.+r")>;
802 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedExynosM5.td716 def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT.+r")>;
840 def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedThunderX2T99.td1188 (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>;
1414 (instregex "^FRINT[AIMNPXZ](v2f32)")>;
1417 (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
H A DAArch64SchedThunderX3T110.td1295 (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>;
1521 (instregex "^FRINT[AIMNPXZ](v2f32)")>;
1524 (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
H A DAArch64SchedKryoDetails.td963 (instregex "FRINT(A|I|M|N|P|X|Z)(S|D)r")>;
969 (instregex "FRINT(A|I|M|N|P|X|Z)v2f32")>;
975 (instregex "FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)")>;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp501 case Intrinsic::rint: Opcode = ISD::FRINT; break; in mightUseCTR()
610 Opcode = ISD::FRINT; break; in mightUseCTR()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp208 case ISD::FRINT: return "frint"; in getOperationName()
H A DLegalizeFloatTypes.cpp117 case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break; in SoftenFloatResult()
1257 case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break; in ExpandFloatResult()
2268 case ISD::FRINT: in PromoteFloatResult()
2633 case ISD::FRINT: in SoftPromoteHalfResult()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp297 ISD::FFLOOR, ISD::FRINT, ISD::FTRUNC, ISD::FMINNUM, in AMDGPUTargetLowering()
400 ISD::FMUL, ISD::FMA, ISD::FRINT, ISD::FNEARBYINT, in AMDGPUTargetLowering()
509 case ISD::FRINT: in fnegFoldsIntoOp()
1158 case ISD::FRINT: return LowerFRINT(Op, DAG); in LowerOperation()
2146 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0)); in LowerFNEARBYINT()
3846 case ISD::FRINT: in performFNegCombine()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-fp-rounding.ll190 ; FRINT
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp145 setOperationAction(ISD::FRINT, MVT::f16, Promote); in MipsSETargetLowering()
387 setOperationAction(ISD::FRINT, Ty, Legal); in addMSAFloatType()
1909 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp129 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
239 ISD::FEXP, ISD::FEXP2, ISD::FRINT}) in WebAssemblyTargetLowering()

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