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Searched refs:FP_ROUND (Results 1 – 25 of 38) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dfp-double-rounding.ll26 ; Hack, to generate a precise FP_ROUND to double
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dneon_fpconv.ll3 ; PR12540: ARM backend lowering of FP_ROUND v2f64 to v2f32.
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def62 DAG_INSTRUCTION(FPTrunc, 1, 1, experimental_constrained_fptrunc, FP_ROUND)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h852 FP_ROUND, enumerator
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp1798 { ISD::FP_ROUND, MVT::nxv2f16, MVT::nxv2f32, 1 }, in getCastInstrCost()
1799 { ISD::FP_ROUND, MVT::nxv4f16, MVT::nxv4f32, 1 }, in getCastInstrCost()
1800 { ISD::FP_ROUND, MVT::nxv8f16, MVT::nxv8f32, 3 }, in getCastInstrCost()
1803 { ISD::FP_ROUND, MVT::nxv2f16, MVT::nxv2f64, 1 }, in getCastInstrCost()
1804 { ISD::FP_ROUND, MVT::nxv4f16, MVT::nxv4f64, 3 }, in getCastInstrCost()
1805 { ISD::FP_ROUND, MVT::nxv8f16, MVT::nxv8f64, 7 }, in getCastInstrCost()
1808 { ISD::FP_ROUND, MVT::nxv2f32, MVT::nxv2f64, 1 }, in getCastInstrCost()
1809 { ISD::FP_ROUND, MVT::nxv4f32, MVT::nxv4f64, 3 }, in getCastInstrCost()
1810 { ISD::FP_ROUND, MVT::nxv8f32, MVT::nxv8f64, 6 }, in getCastInstrCost()
H A DAArch64ISelLowering.cpp482 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); in AArch64TargetLowering()
483 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in AArch64TargetLowering()
484 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in AArch64TargetLowering()
1316 setOperationAction(ISD::FP_ROUND, VT, Custom); in AArch64TargetLowering()
1385 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Custom); in AArch64TargetLowering()
1391 setOperationAction(ISD::FP_ROUND, VT, Custom); in AArch64TargetLowering()
1658 setOperationAction(ISD::FP_ROUND, VT, Custom); in addTypeForFixedLengthSVE()
4055 ISD::FP_ROUND, dl, MVT::f16, in LowerINT_TO_FP()
5439 case ISD::FP_ROUND: in LowerOperation()
17580 if (DCI.isBeforeLegalizeOps() && Value.getOpcode() == ISD::FP_ROUND && in performSTORECombine()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp108 case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break; in SoftenFloatResult()
839 case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break; in SoftenFloatOperand()
887 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 || in SoftenFloatOp_FP_ROUND()
1074 Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(), in SoftenFloatOp_STORE()
1796 case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break; in ExpandFloatOperand()
1906 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ExpandFloatOp_FP_ROUND()
2293 case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break; in PromoteFloatResult()
2535 DAG.getNode(ISD::FP_ROUND, DL, VT, NV, DAG.getIntPtrConstant(0, DL))); in PromoteFloatRes_XINT_TO_FP()
2617 case ISD::FP_ROUND: R = SoftPromoteHalfRes_FP_ROUND(N); break; in SoftPromoteHalfResult()
H A DLegalizeVectorTypes.cpp57 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
344 return DAG.getNode(ISD::FP_ROUND, DL, in ScalarizeVecRes_FP_ROUND()
674 case ISD::FP_ROUND: in ScalarizeVectorOperand()
848 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecOp_FP_ROUND()
1031 case ISD::FP_ROUND: in SplitVectorResult()
2155 if (Opcode == ISD::FP_ROUND) { in SplitVecRes_UnaryOp()
2702 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; in SplitVectorOperand()
3513 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec, in SplitVecOp_TruncateHelper()
3809 case ISD::FP_ROUND: in WidenVectorResult()
5454 case ISD::FP_ROUND: in WidenVectorOperand()
[all …]
H A DLegalizeDAG.cpp2879 case ISD::FP_ROUND: in ExpandNode()
3254 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op, in ExpandNode()
4326 case ISD::FP_ROUND: in ConvertNodeToLibcall()
4629 TruncOp = ISD::FP_ROUND; in PromoteNode()
4638 if (TruncOp != ISD::FP_ROUND) in PromoteNode()
4698 Tmp1 = DAG.getNode(ISD::FP_ROUND, dl, OVT, Tmp1, in PromoteNode()
4759 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4788 DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4820 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4853 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
H A DLegalizeVectorOps.cpp384 case ISD::FP_ROUND: in LegalizeOp()
558 case ISD::FP_ROUND: in Promote()
597 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, DAG.getIntPtrConstant(0, dl)); in Promote()
H A DSelectionDAGDumper.cpp347 case ISD::FP_ROUND: return "fp_round"; in getOperationName()
H A DDAGCombiner.cpp1767 case ISD::FP_ROUND: return visitFP_ROUND(N); in visit()
11669 CastOpcode == ISD::FP_ROUND) && in matchVSelectOpSizesWithSetCC()
11695 if (CastOpcode == ISD::FP_ROUND) { in matchVSelectOpSizesWithSetCC()
15281 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
15410 N1.getOpcode() == ISD::FP_ROUND)) { in CanCombineFCOPYSIGN_EXTEND_ROUND()
15763 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
15810 N->use_begin()->getOpcode() == ISD::FP_ROUND) in visitFP_EXTEND()
15824 if (N0.getOpcode() == ISD::FP_ROUND in visitFP_EXTEND()
15829 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, in visitFP_EXTEND()
15844 DAG.getNode(ISD::FP_ROUND, SDLoc(N0), in visitFP_EXTEND()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp290 case ISD::FP_ROUND: in getCastInstrCost()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp587 {ISD::FP_ROUND, MVT::v4f32, MVT::v4f16, 1}, in getCastInstrCost()
588 {ISD::FP_ROUND, MVT::v8f32, MVT::v8f16, 3}, in getCastInstrCost()
627 ((ISD == ISD::FP_ROUND && SrcTy.getScalarType() == MVT::f64 && in getCastInstrCost()
633 {ISD::FP_ROUND, MVT::v2f64, 2}, in getCastInstrCost()
821 if (ISD == ISD::FP_ROUND || ISD == ISD::FP_EXTEND) { in getCastInstrCost()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp174 ISD::FP_ROUND, ISD::CONCAT_VECTORS}); in WebAssemblyTargetLowering()
2516 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
2555 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
2599 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
2746 case ISD::FP_ROUND: in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1827 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1855 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1856 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
3171 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2461 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2501 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3869 case ISD::FP_ROUND: { in performFNegCombine()
3874 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3883 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
H A DR600ISelLowering.cpp199 setTargetDAGCombine({ISD::FP_ROUND, ISD::FP_TO_SINT, ISD::EXTRACT_VECTOR_ELT, in R600TargetLowering()
1707 case ISD::FP_ROUND: { in PerformDAGCombine()
H A DSIISelLowering.cpp213 setOperationAction(ISD::FP_ROUND, in SITargetLowering()
493 {ISD::FP_ROUND, ISD::FCOS, ISD::FSIN, ISD::FROUND, ISD::FPTRUNC_ROUND}, in SITargetLowering()
4686 case ISD::FP_ROUND: in LowerOperation()
5286 DAG.getNode(ISD::FP_ROUND, DL, VT, Op, in getFPExtOrFPRound()
8934 SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag); in LowerFDIV16()
9346 Cvt = DAG.getNode(ISD::FP_ROUND, DL, VT, Cvt, in performUCharToFloatCombine()
10029 case ISD::FP_ROUND: in isCanonicalized()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-split-fcvt.ll94 ; FP_ROUND
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1047 case ISD::FP_ROUND: in PreprocessISelDAG()
1061 case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break; in PreprocessISelDAG()
1276 case ISD::FP_ROUND: in PreprocessISelDAG()
1307 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
H A DX86TargetTransformInfo.cpp1791 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, in getCastInstrCost()
2171 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, in getCastInstrCost()
2301 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, in getCastInstrCost()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1210 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in PPCTargetLowering()
1211 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
1261 setOperationAction(ISD::FP_ROUND, VT, Custom); in PPCTargetLowering()
8663 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
8744 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
9041 (V->getOperand(i).getOpcode() == ISD::FP_ROUND && in haveEfficientBuildVectorPattern()
11201 case ISD::FP_ROUND: in LowerOperation()
14066 SDValue Trunc = DAG.getNode(ISD::FP_ROUND, dl, in combineElementTruncationToVectorTruncation()
14111 if (FirstInput.getOpcode() == ISD::FP_ROUND && in combineBVOfConsecutiveLoads()
14544 FP = DAG.getNode(ISD::FP_ROUND, dl, in combineFPToIntToFP()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp155 setOperationAction(ISD::FP_ROUND, MVT::v64f16, Legal); in initializeHVXLowering()
158 setOperationAction(ISD::FP_ROUND, MVT::v64f16, Legal); in initializeHVXLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1820 case FPTrunc: return ISD::FP_ROUND; in InstructionOpcodeToISD()

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