| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 2075 return ISD::FP16_TO_FP; in GetPromotionOpcode()
2240 case ISD::FP16_TO_FP: in PromoteFloatResult()
2756 Op0 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op0); in SoftPromoteHalfRes_FMAD()
2757 Op1 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op1); in SoftPromoteHalfRes_FMAD()
2758 Op2 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op2); in SoftPromoteHalfRes_FMAD()
2772 Op0 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op0); in SoftPromoteHalfRes_FPOWI()
2843 Op = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op); in SoftPromoteHalfRes_UnaryOp()
2858 Op0 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op0); in SoftPromoteHalfRes_BinOp()
2859 Op1 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op1); in SoftPromoteHalfRes_BinOp()
2953 Op1 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op1); in SoftPromoteHalfOp_FCOPYSIGN()
[all …]
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| H A D | SelectionDAGDumper.cpp | 364 case ISD::FP16_TO_FP: return "fp16_to_fp"; in getOperationName()
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| H A D | LegalizeDAG.cpp | 908 Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result); in LegalizeLoadOps()
3219 case ISD::FP16_TO_FP: in ExpandNode()
3225 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0)); in ExpandNode()
4213 case ISD::FP16_TO_FP: in ConvertNodeToLibcall()
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| H A D | LegalizeIntegerTypes.cpp | 1666 case ISD::FP16_TO_FP: in PromoteIntegerOperand()
3398 Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op); in ExpandIntRes_FP_TO_SINT()
3430 Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op); in ExpandIntRes_FP_TO_UINT()
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| H A D | DAGCombiner.cpp | 1796 case ISD::FP16_TO_FP: return visitFP16_TO_FP(N); in visit()
15818 if (N0.getOpcode() == ISD::FP16_TO_FP && in visitFP_EXTEND()
15819 TLI.getOperationAction(ISD::FP16_TO_FP, VT) == TargetLowering::Legal) in visitFP_EXTEND()
15820 return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), VT, N0.getOperand(0)); in visitFP_EXTEND()
23292 if (N0->getOpcode() == ISD::FP16_TO_FP) in visitFP_TO_FP16()
23305 return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), N->getValueType(0), in visitFP16_TO_FP()
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| H A D | SelectionDAG.cpp | 5033 case ISD::FP16_TO_FP: in getNode()
5036 APFloat FPV(Opcode == ISD::FP16_TO_FP ? APFloat::IEEEhalf() in getNode()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 896 FP16_TO_FP, enumerator
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 328 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in AMDGPUTargetLowering()
2705 (SrcVT == MVT::f32 && Src.getOpcode() == ISD::FP16_TO_FP)) { in LowerFP_TO_INT()
3885 case ISD::FP16_TO_FP: { in performFNegCombine()
3897 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg); in performFNegCombine()
3913 case ISD::FP16_TO_FP: { in performFAbsCombine()
3922 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs); in performFAbsCombine()
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| H A D | SIISelLowering.cpp | 475 setOperationAction(ISD::FP16_TO_FP, MVT::i16, Promote); in SITargetLowering()
476 AddPromotedToType(ISD::FP16_TO_FP, MVT::i16, MVT::i32); in SITargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1620 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in SparcTargetLowering()
1622 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in SparcTargetLowering()
1624 setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand); in SparcTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1776 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in HexagonTargetLowering()
1777 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in HexagonTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 437 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in MipsTargetLowering()
439 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in MipsTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 135 setOperationAction(ISD::FP16_TO_FP, T, Expand); in WebAssemblyTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 216 setOperationAction(ISD::FP16_TO_FP, FPVT, Expand); in initSPUActions()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 518 def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>;
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 204 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in PPCTargetLowering()
207 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in PPCTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1460 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in ARMTargetLowering()
1466 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in ARMTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 317 ISD::FREM, ISD::FP16_TO_FP, ISD::FP_TO_FP16}; in RISCVTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 401 for (auto Op : {ISD::FP16_TO_FP, ISD::STRICT_FP16_TO_FP, ISD::FP_TO_FP16, in X86TargetLowering()
2370 ISD::FP16_TO_FP, in X86TargetLowering()
32268 case ISD::FP16_TO_FP: in LowerOperation()
55195 case ISD::FP16_TO_FP: return combineFP16_TO_FP(N, DAG, Subtarget); in PerformDAGCombine()
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