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Searched refs:FMAD (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dfmad-formation-fmul-distribute-denormal-mode.ll49 ; FMAD: ; %bb.0:
52 ; FMAD-NEXT: s_setpc_b64 s[30:31]
94 ; FMAD: ; %bb.0:
97 ; FMAD-NEXT: s_setpc_b64 s[30:31]
143 ; FMAD: ; %bb.0:
147 ; FMAD-NEXT: s_setpc_b64 s[30:31]
195 ; FMAD: ; %bb.0:
199 ; FMAD-NEXT: s_setpc_b64 s[30:31]
242 ; FMAD: ; %bb.0:
245 ; FMAD-NEXT: s_setpc_b64 s[30:31]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-fmad.s32.mir26 ; GFX6-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
27 ; GFX6-NEXT: $vgpr0 = COPY [[FMAD]](s32)
35 ; GFX7-NEXT: $vgpr0 = COPY [[FMAD]](s32)
43 ; GFX101-NEXT: $vgpr0 = COPY [[FMAD]](s32)
78 ; GFX6-NEXT: $vgpr0 = COPY [[FMAD]](s32)
86 ; GFX7-NEXT: $vgpr0 = COPY [[FMAD]](s32)
94 ; GFX101-NEXT: $vgpr0 = COPY [[FMAD]](s32)
131 ; GFX6-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[UV]], [[UV2]], [[UV4]]
144 ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[UV]], [[UV2]], [[UV4]]
203 ; GFX6-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[UV]], [[UV3]], [[UV6]]
[all …]
H A Dcombine-redundant-neg.mir118 ; CHECK-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
119 ; CHECK-NEXT: $vgpr0 = COPY [[FMAD]](s32)
H A Dcombine-foldable-fneg.mir216 ; CHECK-NEXT: [[FMAD:%[0-9]+]]:_(s32) = nsz G_FMAD [[COPY]], [[FNEG]], [[FNEG1]]
217 ; CHECK-NEXT: $vgpr0 = COPY [[FMAD]](s32)
644 ; CHECK-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
645 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMAD]]
H A Dlegalize-fmad.s16.mir46 ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(s16) = G_FMAD [[TRUNC]], [[TRUNC1]], [[TRUNC2]]
47 ; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMAD]](s16)
144 ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(s16) = G_FMAD [[TRUNC]], [[TRUNC2]], [[TRUNC4]]
146 ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FMAD]](s16)
309 ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(s16) = G_FMAD [[TRUNC]], [[TRUNC4]], [[TRUNC8]]
313 ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FMAD]](s16)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h486 FMAD, enumerator
H A DTargetLowering.h2963 return isOperationLegal(ISD::FMAD, N->getValueType(0)); in isFMADLegal()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCodeGenPrepare.cpp965 auto FMAD = !ST->hasMadMacF32Insts() in expandDivRem24Impl() local
968 Value *FR = Builder.CreateIntrinsic(FMAD, in expandDivRem24Impl()
H A DAMDGPUISelLowering.cpp502 case ISD::FMAD: in fnegFoldsIntoOp()
735 case ISD::FMAD: { in getNegatedExpression()
1640 (unsigned)ISD::FMAD : in LowerDIVREM24()
1727 unsigned FMAD = !Subtarget->hasMadMacF32Insts() ? in LowerUDIVREM64() local
1730 (unsigned)ISD::FMAD : in LowerUDIVREM64()
1735 SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi, in LowerUDIVREM64()
1744 SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc, in LowerUDIVREM64()
3766 case ISD::FMAD: { in performFNegCombine()
H A DAMDGPUISelDAGToDAG.cpp191 case ISD::FMAD: in fp16SrcZerosHighBits()
680 case ISD::FMAD: in Select()
H A DSIISelLowering.cpp398 setOperationAction(ISD::FMAD, MVT::f32, Legal); in SITargetLowering()
510 setOperationAction(ISD::FMAD, MVT::f16, Legal); in SITargetLowering()
791 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) || in isFPExtFoldable()
10025 case ISD::FMAD: in isCanonicalized()
10788 isOperationLegal(ISD::FMAD, VT)) in getFusedOpcode()
10789 return ISD::FMAD; in getFusedOpcode()
H A DR600ISelLowering.cpp159 setOperationAction(ISD::FMAD, MVT::f32, Legal); in R600TargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp267 case ISD::FMAD: return "fmad"; in getOperationName()
H A DLegalizeFloatTypes.cpp2289 case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break; in PromoteFloatResult()
2654 case ISD::FMAD: R = SoftPromoteHalfRes_FMAD(N); break; in SoftPromoteHalfResult()
H A DDAGCombiner.cpp14004 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFADDForFMACombine()
14009 return Opcode == ISD::FMA || Opcode == ISD::FMAD; in visitFADDForFMACombine()
14217 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFSUBForFMACombine()
14367 return Opcode == ISD::FMA || Opcode == ISD::FMAD; in visitFSUBForFMACombine()
14533 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFMULForFMADistributiveCombine()
H A DLegalizeDAG.cpp3216 case ISD::FMAD: in ExpandNode()
H A DTargetLowering.cpp6862 case ISD::FMAD: { in getNegatedExpression()
H A DSelectionDAG.cpp4654 case ISD::FMAD: { in isKnownNeverNaN()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp798 ISD::FMAD, ISD::SMIN, in initActions()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td472 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp, [SDNPCommutative]>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedNeoverseN2.td1979 "^(FMAD|FNMAD|FNML[AS]|FN?MSB)_ZPmZZ_[HSD]$")>;
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-intrinsics-fp-arith.ll334 ; FMAD
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp43654 case ISD::FMAD: in scalarizeExtEltFP()