| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 80 DAG_FUNCTION(log2, 1, 1, experimental_constrained_log2, FLOG2)
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 920 FLOG2, enumerator
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| H A D | BasicTTIImpl.h | 1706 ISD = ISD::FLOG2; in getTypeBasedIntrinsicInstrCost()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 222 case ISD::FLOG2: return "flog2"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 95 case ISD::FLOG2: R = SoftenFloatRes_FLOG2(N); break; in SoftenFloatResult()
1239 case ISD::FLOG2: ExpandFloatRes_FLOG2(N, Lo, Hi); break; in ExpandFloatResult()
2264 case ISD::FLOG2: in PromoteFloatResult()
2628 case ISD::FLOG2: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 373 case ISD::FLOG2: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 92 case ISD::FLOG2: in ScalarizeVectorResult()
1024 case ISD::FLOG2: in SplitVectorResult()
3841 case ISD::FLOG2: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4041 case ISD::FLOG2: in ConvertNodeToLibcall()
4846 case ISD::FLOG2: in PromoteNode()
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| H A D | SelectionDAGBuilder.cpp | 5214 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op, Flags); in expandLog2()
8323 if (visitUnaryFloatCall(I, ISD::FLOG2)) in visitCall()
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| H A D | SelectionDAG.cpp | 4663 case ISD::FLOG2: in isKnownNeverNaN()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 152 setOperationAction(ISD::FLOG2, MVT::f16, Promote); in MipsSETargetLowering()
384 setOperationAction(ISD::FLOG2, Ty, Legal); in addMSAFloatType()
1891 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsISelLowering.cpp | 428 setOperationAction(ISD::FLOG2, MVT::f32, Expand); in MipsTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 296 setOperationAction({ISD::FCEIL, ISD::FEXP2, ISD::FPOW, ISD::FLOG2, ISD::FABS, in AMDGPUTargetLowering()
398 ISD::FEXP, ISD::FLOG2, ISD::FREM, ISD::FLOG, in AMDGPUTargetLowering()
2214 SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand); in LowerFLOG()
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| H A D | AMDGPUISelDAGToDAG.cpp | 159 case ISD::FLOG2: in fp16SrcZerosHighBits()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 887 setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, ISD::FEXP, in initActions()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 238 for (auto Op : {ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, in WebAssemblyTargetLowering()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 494 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 369 setOperationAction(ISD::FLOG2, VT, Expand); in addMVEVectorTypes()
878 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); in ARMTargetLowering()
899 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand); in ARMTargetLowering()
915 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand); in ARMTargetLowering()
1048 setOperationAction(ISD::FLOG2, MVT::f64, Expand); in ARMTargetLowering()
1528 setOperationAction(ISD::FLOG2, MVT::f16, Promote); in ARMTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1636 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2, in HexagonTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 335 ISD::FLOG2, ISD::FLOG10}, in RISCVTargetLowering()
676 setOperationAction(ISD::FLOG2, VT, Expand); in RISCVTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 593 ISD::FLOG2, ISD::FLOG10, ISD::STRICT_FREM, in AArch64TargetLowering()
1333 setOperationAction(ISD::FLOG2, VT, Expand); in AArch64TargetLowering()
1468 setOperationAction(ISD::FLOG2, VT, Expand); in addTypeForNEON()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 836 setOperationAction(ISD::FLOG2, VT, Expand); in PPCTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 574 setOperationAction(ISD::FLOG2, VT, Action); in X86TargetLowering()
884 setOperationAction(ISD::FLOG2, MVT::f80, Expand); in X86TargetLowering()
902 setOperationAction(ISD::FLOG2, VT, Expand); in X86TargetLowering()
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