| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 75 DAG_FUNCTION(exp2, 1, 1, experimental_constrained_exp2, FEXP2)
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 923 FEXP2, enumerator
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| H A D | BasicTTIImpl.h | 1697 ISD = ISD::FEXP2; in getTypeBasedIntrinsicInstrCost()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 218 case ISD::FEXP2: return "fexp2"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 89 case ISD::FEXP2: R = SoftenFloatRes_FEXP2(N); break; in SoftenFloatResult()
1233 case ISD::FEXP2: ExpandFloatRes_FEXP2(N, Lo, Hi); break; in ExpandFloatResult()
2261 case ISD::FEXP2: in PromoteFloatResult()
2625 case ISD::FEXP2: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 376 case ISD::FEXP2: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 88 case ISD::FEXP2: in ScalarizeVectorResult()
1020 case ISD::FEXP2: in SplitVectorResult()
3837 case ISD::FEXP2: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4056 case ISD::FEXP2: in ConvertNodeToLibcall()
4850 case ISD::FEXP2: in PromoteNode()
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| H A D | SelectionDAGBuilder.cpp | 5316 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op, Flags); in expandExp2()
8329 if (visitUnaryFloatCall(I, ISD::FEXP2)) in visitCall()
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| H A D | SelectionDAG.cpp | 4624 case ISD::FEXP2: in isKnownNeverNaN()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 150 setOperationAction(ISD::FEXP2, MVT::f16, Promote); in MipsSETargetLowering()
383 setOperationAction(ISD::FEXP2, Ty, Legal); in addMSAFloatType()
1887 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsMSAInstrInfo.td | 2047 // 1.0 when we only need to match ISD::FEXP2.
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 296 setOperationAction({ISD::FCEIL, ISD::FEXP2, ISD::FPOW, ISD::FLOG2, ISD::FABS, in AMDGPUTargetLowering()
397 ISD::FCEIL, ISD::FCOS, ISD::FDIV, ISD::FEXP2, in AMDGPUTargetLowering()
2228 return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags()); in lowerFEXP()
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| H A D | AMDGPUISelDAGToDAG.cpp | 162 case ISD::FEXP2: in fp16SrcZerosHighBits()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 888 ISD::FEXP2, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in initActions()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 239 ISD::FEXP, ISD::FEXP2, ISD::FRINT}) in WebAssemblyTargetLowering()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 492 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 372 setOperationAction(ISD::FEXP2, VT, Expand); in addMVEVectorTypes()
881 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); in ARMTargetLowering()
902 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand); in ARMTargetLowering()
918 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand); in ARMTargetLowering()
1051 setOperationAction(ISD::FEXP2, MVT::f64, Expand); in ARMTargetLowering()
1525 setOperationAction(ISD::FEXP2, MVT::f16, Promote); in ARMTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1637 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC, in HexagonTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 334 ISD::FSINCOS, ISD::FEXP, ISD::FEXP2, ISD::FLOG, in RISCVTargetLowering()
674 setOperationAction(ISD::FEXP2, VT, Expand); in RISCVTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 592 ISD::FEXP, ISD::FEXP2, ISD::FLOG, in AArch64TargetLowering()
1331 setOperationAction(ISD::FEXP2, VT, Expand); in AArch64TargetLowering()
1471 setOperationAction(ISD::FEXP2, VT, Expand); in addTypeForNEON()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 838 setOperationAction(ISD::FEXP2, VT, Expand); in PPCTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 577 setOperationAction(ISD::FEXP2, VT, Action); in X86TargetLowering()
887 setOperationAction(ISD::FEXP2, MVT::f80, Expand); in X86TargetLowering()
905 setOperationAction(ISD::FEXP2, VT, Expand); in X86TargetLowering()
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