| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 74 DAG_FUNCTION(exp, 1, 1, experimental_constrained_exp, FEXP)
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 922 FEXP, enumerator
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| H A D | BasicTTIImpl.h | 1694 ISD = ISD::FEXP; in getTypeBasedIntrinsicInstrCost()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 216 case ISD::FEXP: return "fexp"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 87 case ISD::FEXP: R = SoftenFloatRes_FEXP(N); break; in SoftenFloatResult()
1231 case ISD::FEXP: ExpandFloatRes_FEXP(N, Lo, Hi); break; in ExpandFloatResult()
2260 case ISD::FEXP: in PromoteFloatResult()
2624 case ISD::FEXP: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 375 case ISD::FEXP: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 87 case ISD::FEXP: in ScalarizeVectorResult()
1019 case ISD::FEXP: in SplitVectorResult()
3836 case ISD::FEXP: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4051 case ISD::FEXP: in ConvertNodeToLibcall()
4849 case ISD::FEXP: in PromoteNode()
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| H A D | SelectionDAG.cpp | 4623 case ISD::FEXP: in isKnownNeverNaN()
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| H A D | SelectionDAGBuilder.cpp | 5018 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op, Flags); in expandExp()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 303 setOperationAction({ISD::FLOG, ISD::FLOG10, ISD::FEXP}, MVT::f32, Custom); in AMDGPUTargetLowering()
398 ISD::FEXP, ISD::FLOG2, ISD::FREM, ISD::FLOG, in AMDGPUTargetLowering()
1166 case ISD::FEXP: in LowerOperation()
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| H A D | AMDGPUISelDAGToDAG.cpp | 161 case ISD::FEXP: in fp16SrcZerosHighBits()
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| H A D | SIISelLowering.cpp | 394 setOperationAction({ISD::FLOG, ISD::FEXP, ISD::FLOG10}, MVT::f16, Custom); in SITargetLowering()
667 setOperationAction(ISD::FEXP, MVT::v2f16, Custom); in SITargetLowering()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 887 setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, ISD::FEXP, in initActions()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 239 ISD::FEXP, ISD::FEXP2, ISD::FRINT}) in WebAssemblyTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 371 setOperationAction(ISD::FEXP, VT, Expand); in addMVEVectorTypes()
880 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); in ARMTargetLowering()
901 setOperationAction(ISD::FEXP, MVT::v4f32, Expand); in ARMTargetLowering()
917 setOperationAction(ISD::FEXP, MVT::v2f32, Expand); in ARMTargetLowering()
1050 setOperationAction(ISD::FEXP, MVT::f64, Expand); in ARMTargetLowering()
1524 setOperationAction(ISD::FEXP, MVT::f16, Promote); in ARMTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1637 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC, in HexagonTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 149 setOperationAction(ISD::FEXP, MVT::f16, Promote); in MipsSETargetLowering()
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| H A D | MipsISelLowering.cpp | 430 setOperationAction(ISD::FEXP, MVT::f32, Expand); in MipsTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 401 setOperationAction(ISD::FEXP, MVT::f64, Custom); in PPCTargetLowering()
407 setOperationAction(ISD::FEXP, MVT::f32, Custom); in PPCTargetLowering()
837 setOperationAction(ISD::FEXP, VT, Expand); in PPCTargetLowering()
11141 case ISD::FEXP: return lowerExp(Op, DAG); in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 334 ISD::FSINCOS, ISD::FEXP, ISD::FEXP2, ISD::FLOG, in RISCVTargetLowering()
673 setOperationAction(ISD::FEXP, VT, Expand); in RISCVTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 592 ISD::FEXP, ISD::FEXP2, ISD::FLOG, in AArch64TargetLowering()
1330 setOperationAction(ISD::FEXP, VT, Expand); in AArch64TargetLowering()
1470 setOperationAction(ISD::FEXP, VT, Expand); in addTypeForNEON()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 576 setOperationAction(ISD::FEXP, VT, Action); in X86TargetLowering()
886 setOperationAction(ISD::FEXP, MVT::f80, Expand); in X86TargetLowering()
904 setOperationAction(ISD::FEXP, VT, Expand); in X86TargetLowering()
2314 ISD::FEXP, ISD::STRICT_FEXP, in X86TargetLowering()
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