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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dfloat_arithmetic_operations.mir116 ; FP32: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[COPY]], [[COPY1]]
117 ; FP32: $f0 = COPY [[FDIV]](s32)
123 ; FP64: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[COPY]], [[COPY1]]
124 ; FP64: $f0 = COPY [[FDIV]](s32)
232 ; FP32: [[FDIV:%[0-9]+]]:_(s64) = G_FDIV [[COPY]], [[COPY1]]
233 ; FP32: $d0 = COPY [[FDIV]](s64)
239 ; FP64: [[FDIV:%[0-9]+]]:_(s64) = G_FDIV [[COPY]], [[COPY1]]
240 ; FP64: $d0 = COPY [[FDIV]](s64)
H A Dfloating_point_vec_arithmetic_operations.mir201 ; P5600: [[FDIV:%[0-9]+]]:_(<4 x s32>) = G_FDIV [[LOAD]], [[LOAD1]]
202 ; P5600: G_STORE [[FDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
229 ; P5600: [[FDIV:%[0-9]+]]:_(<2 x s64>) = G_FDIV [[LOAD]], [[LOAD1]]
230 ; P5600: G_STORE [[FDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
H A Dfloating_point_vec_arithmetic_operations_builtin.mir213 ; P5600: [[FDIV:%[0-9]+]]:_(<4 x s32>) = G_FDIV [[LOAD]], [[LOAD1]]
214 ; P5600: G_STORE [[FDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
241 ; P5600: [[FDIV:%[0-9]+]]:_(<2 x s64>) = G_FDIV [[LOAD]], [[LOAD1]]
242 ; P5600: G_STORE [[FDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dfloat_arithmetic_operations.mir120 ; FP32: [[FDIV:%[0-9]+]]:fprb(s32) = G_FDIV [[COPY]], [[COPY1]]
121 ; FP32: $f0 = COPY [[FDIV]](s32)
127 ; FP64: [[FDIV:%[0-9]+]]:fprb(s32) = G_FDIV [[COPY]], [[COPY1]]
128 ; FP64: $f0 = COPY [[FDIV]](s32)
240 ; FP32: [[FDIV:%[0-9]+]]:fprb(s64) = G_FDIV [[COPY]], [[COPY1]]
241 ; FP32: $d0 = COPY [[FDIV]](s64)
247 ; FP64: [[FDIV:%[0-9]+]]:fprb(s64) = G_FDIV [[COPY]], [[COPY1]]
248 ; FP64: $d0 = COPY [[FDIV]](s64)
H A Dfloating_point_vec_arithmetic_operations.mir208 ; P5600: [[FDIV:%[0-9]+]]:fprb(<4 x s32>) = G_FDIV [[LOAD]], [[LOAD1]]
209 ; P5600: G_STORE [[FDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
237 ; P5600: [[FDIV:%[0-9]+]]:fprb(<2 x s64>) = G_FDIV [[LOAD]], [[LOAD1]]
238 ; P5600: G_STORE [[FDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dlegalize-fdiv-scalar.mir41 ; CHECK: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[TRUNC]], [[TRUNC1]]
42 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FDIV]](s32)
80 ; CHECK: [[FDIV:%[0-9]+]]:_(s64) = G_FDIV [[TRUNC]], [[TRUNC1]]
81 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FDIV]](s64)
/llvm-project-15.0.7/lldb/test/Shell/Register/
H A Dx86-64-fp-read.test13 # CHECK: (void *) $0 = [[FDIV:0x[0-9a-f]*]]
22 # CHECK-DAG: fip = [[FDIV]]
36 # CHECK: (void *) $2 = [[FDIV]]
H A Dx86-fp-read.test13 # CHECK: (void *) $0 = [[FDIV:0x[0-9a-f]*]]
22 # CHECK-DAG: fioff = [[FDIV]]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-fp-arith.mir25 ; CHECK: [[FDIV:%[0-9]+]]:_(<2 x s32>) = G_FDIV [[COPY]], [[COPY1]]
26 ; CHECK: $d0 = COPY [[FDIV]](<2 x s32>)
H A Dlegalize-fp-arith-fp16.mir112 ; NO-FP16: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[FPEXT]], [[FPEXT1]]
113 ; NO-FP16: %op:_(s16) = G_FPTRUNC [[FDIV]](s32)
H A Dregbankselect-default.mir635 ; CHECK: [[FDIV:%[0-9]+]]:fpr(s32) = G_FDIV [[COPY]], [[COPY]]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-redundant-neg.mir96 ; CHECK-NEXT: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[COPY]], [[COPY1]]
97 ; CHECK-NEXT: $vgpr0 = COPY [[FDIV]](s32)
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp295 { ISD::FDIV, MVT::f32, 18 }, // divss in getArithmeticInstrCost()
296 { ISD::FDIV, MVT::v4f32, 35 }, // divps in getArithmeticInstrCost()
297 { ISD::FDIV, MVT::f64, 33 }, // divsd in getArithmeticInstrCost()
298 { ISD::FDIV, MVT::v2f64, 65 }, // divpd in getArithmeticInstrCost()
312 { ISD::FDIV, MVT::f32, 17 }, // divss in getArithmeticInstrCost()
313 { ISD::FDIV, MVT::v4f32, 39 }, // divps in getArithmeticInstrCost()
314 { ISD::FDIV, MVT::f64, 32 }, // divsd in getArithmeticInstrCost()
315 { ISD::FDIV, MVT::v2f64, 69 }, // divpd in getArithmeticInstrCost()
952 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
953 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
H A DX86IntrinsicsInfo.h443 X86_INTRINSIC_DATA(avx512_div_pd_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
444 X86_INTRINSIC_DATA(avx512_div_ps_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
993 X86_INTRINSIC_DATA(avx512fp16_div_ph_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPNodes.def115 ADD_BINARY_VVP_OP_COMPACT(FDIV)
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def55 DAG_INSTRUCTION(FDiv, 2, 1, experimental_constrained_fdiv, FDIV)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h393 FDIV, enumerator
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-fp-reciprocal.ll4 ; FDIV
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.h503 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); } in visitFDiv()
H A DSelectionDAGDumper.cpp263 case ISD::FDIV: return "fdiv"; in getOperationName()
H A DLegalizeFloatTypes.cpp85 case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break; in SoftenFloatResult()
1229 case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break; in ExpandFloatResult()
2278 case ISD::FDIV: in PromoteFloatResult()
2643 case ISD::FDIV: in SoftPromoteHalfResult()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td36 defm FDIV : ADDS_MMM<"div.d", II_DIV_D, 0, fdiv>,
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dfp-arith.ll430 ; FDIV
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp605 case ISD::FDIV: in getArithmeticInstrCost()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td125 defm FDIV : FT_XYZ<0b011000, "fdiv", BinOpFrag<(fdiv node:$LHS, node:$RHS)>>;

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