1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
3--- |
4
5  define void @fadd_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
6  define void @fadd_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
7
8  define void @fsub_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
9  define void @fsub_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
10
11  define void @fmul_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
12  define void @fmul_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
13
14  define void @fdiv_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
15  define void @fdiv_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
16
17...
18---
19name:            fadd_v4f32
20alignment:       4
21legalized:       true
22tracksRegLiveness: true
23body:             |
24  bb.1.entry:
25    liveins: $a0, $a1, $a2
26
27    ; P5600-LABEL: name: fadd_v4f32
28    ; P5600: liveins: $a0, $a1, $a2
29    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
30    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
31    ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
32    ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
33    ; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
34    ; P5600: [[FADD:%[0-9]+]]:fprb(<4 x s32>) = G_FADD [[LOAD]], [[LOAD1]]
35    ; P5600: G_STORE [[FADD]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
36    ; P5600: RetRA
37    %0:_(p0) = COPY $a0
38    %1:_(p0) = COPY $a1
39    %2:_(p0) = COPY $a2
40    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
41    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
42    %5:_(<4 x s32>) = G_FADD %3, %4
43    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
44    RetRA
45
46...
47---
48name:            fadd_v2f64
49alignment:       4
50legalized:       true
51tracksRegLiveness: true
52body:             |
53  bb.1.entry:
54    liveins: $a0, $a1, $a2
55
56    ; P5600-LABEL: name: fadd_v2f64
57    ; P5600: liveins: $a0, $a1, $a2
58    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
59    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
60    ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
61    ; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
62    ; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
63    ; P5600: [[FADD:%[0-9]+]]:fprb(<2 x s64>) = G_FADD [[LOAD]], [[LOAD1]]
64    ; P5600: G_STORE [[FADD]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
65    ; P5600: RetRA
66    %0:_(p0) = COPY $a0
67    %1:_(p0) = COPY $a1
68    %2:_(p0) = COPY $a2
69    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
70    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
71    %5:_(<2 x s64>) = G_FADD %3, %4
72    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
73    RetRA
74
75...
76---
77name:            fsub_v4f32
78alignment:       4
79legalized:       true
80tracksRegLiveness: true
81body:             |
82  bb.1.entry:
83    liveins: $a0, $a1, $a2
84
85    ; P5600-LABEL: name: fsub_v4f32
86    ; P5600: liveins: $a0, $a1, $a2
87    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
88    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
89    ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
90    ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
91    ; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
92    ; P5600: [[FSUB:%[0-9]+]]:fprb(<4 x s32>) = G_FSUB [[LOAD]], [[LOAD1]]
93    ; P5600: G_STORE [[FSUB]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
94    ; P5600: RetRA
95    %0:_(p0) = COPY $a0
96    %1:_(p0) = COPY $a1
97    %2:_(p0) = COPY $a2
98    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
99    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
100    %5:_(<4 x s32>) = G_FSUB %3, %4
101    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
102    RetRA
103
104...
105---
106name:            fsub_v2f64
107alignment:       4
108legalized:       true
109tracksRegLiveness: true
110body:             |
111  bb.1.entry:
112    liveins: $a0, $a1, $a2
113
114    ; P5600-LABEL: name: fsub_v2f64
115    ; P5600: liveins: $a0, $a1, $a2
116    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
117    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
118    ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
119    ; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
120    ; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
121    ; P5600: [[FSUB:%[0-9]+]]:fprb(<2 x s64>) = G_FSUB [[LOAD]], [[LOAD1]]
122    ; P5600: G_STORE [[FSUB]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
123    ; P5600: RetRA
124    %0:_(p0) = COPY $a0
125    %1:_(p0) = COPY $a1
126    %2:_(p0) = COPY $a2
127    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
128    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
129    %5:_(<2 x s64>) = G_FSUB %3, %4
130    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
131    RetRA
132
133...
134---
135name:            fmul_v4f32
136alignment:       4
137legalized:       true
138tracksRegLiveness: true
139body:             |
140  bb.1.entry:
141    liveins: $a0, $a1, $a2
142
143    ; P5600-LABEL: name: fmul_v4f32
144    ; P5600: liveins: $a0, $a1, $a2
145    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
146    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
147    ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
148    ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
149    ; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
150    ; P5600: [[FMUL:%[0-9]+]]:fprb(<4 x s32>) = G_FMUL [[LOAD]], [[LOAD1]]
151    ; P5600: G_STORE [[FMUL]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
152    ; P5600: RetRA
153    %0:_(p0) = COPY $a0
154    %1:_(p0) = COPY $a1
155    %2:_(p0) = COPY $a2
156    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
157    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
158    %5:_(<4 x s32>) = G_FMUL %3, %4
159    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
160    RetRA
161
162...
163---
164name:            fmul_v2f64
165alignment:       4
166legalized:       true
167tracksRegLiveness: true
168body:             |
169  bb.1.entry:
170    liveins: $a0, $a1, $a2
171
172    ; P5600-LABEL: name: fmul_v2f64
173    ; P5600: liveins: $a0, $a1, $a2
174    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
175    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
176    ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
177    ; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
178    ; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
179    ; P5600: [[FMUL:%[0-9]+]]:fprb(<2 x s64>) = G_FMUL [[LOAD]], [[LOAD1]]
180    ; P5600: G_STORE [[FMUL]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
181    ; P5600: RetRA
182    %0:_(p0) = COPY $a0
183    %1:_(p0) = COPY $a1
184    %2:_(p0) = COPY $a2
185    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
186    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
187    %5:_(<2 x s64>) = G_FMUL %3, %4
188    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
189    RetRA
190
191...
192---
193name:            fdiv_v4f32
194alignment:       4
195legalized:       true
196tracksRegLiveness: true
197body:             |
198  bb.1.entry:
199    liveins: $a0, $a1, $a2
200
201    ; P5600-LABEL: name: fdiv_v4f32
202    ; P5600: liveins: $a0, $a1, $a2
203    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
204    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
205    ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
206    ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
207    ; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
208    ; P5600: [[FDIV:%[0-9]+]]:fprb(<4 x s32>) = G_FDIV [[LOAD]], [[LOAD1]]
209    ; P5600: G_STORE [[FDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
210    ; P5600: RetRA
211    %0:_(p0) = COPY $a0
212    %1:_(p0) = COPY $a1
213    %2:_(p0) = COPY $a2
214    %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
215    %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
216    %5:_(<4 x s32>) = G_FDIV %3, %4
217    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
218    RetRA
219
220...
221---
222name:            fdiv_v2f64
223alignment:       4
224legalized:       true
225tracksRegLiveness: true
226body:             |
227  bb.1.entry:
228    liveins: $a0, $a1, $a2
229
230    ; P5600-LABEL: name: fdiv_v2f64
231    ; P5600: liveins: $a0, $a1, $a2
232    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
233    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
234    ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
235    ; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
236    ; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
237    ; P5600: [[FDIV:%[0-9]+]]:fprb(<2 x s64>) = G_FDIV [[LOAD]], [[LOAD1]]
238    ; P5600: G_STORE [[FDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
239    ; P5600: RetRA
240    %0:_(p0) = COPY $a0
241    %1:_(p0) = COPY $a1
242    %2:_(p0) = COPY $a2
243    %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
244    %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
245    %5:_(<2 x s64>) = G_FDIV %3, %4
246    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
247    RetRA
248
249...
250