| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 73 DAG_FUNCTION(cos, 1, 1, experimental_constrained_cos, FCOS)
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 916 FCOS, enumerator
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| H A D | BasicTTIImpl.h | 1691 ISD = ISD::FCOS; in getTypeBasedIntrinsicInstrCost()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 94 setOperationAction({ISD::FCOS, ISD::FSIN}, MVT::f32, Custom); in R600TargetLowering()
406 case ISD::FCOS: in LowerOperation()
696 case ISD::FCOS: in LowerTrig()
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| H A D | SIISelLowering.cpp | 452 setOperationAction({ISD::FSIN, ISD::FCOS, ISD::FDIV}, MVT::f32, Custom); in SITargetLowering()
493 {ISD::FP_ROUND, ISD::FCOS, ISD::FSIN, ISD::FROUND, ISD::FPTRUNC_ROUND}, in SITargetLowering()
4659 case ISD::FCOS: in LowerOperation()
9282 case ISD::FCOS: in LowerTrig()
10058 case ISD::FCOS: in isCanonicalized()
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| H A D | AMDGPUISelDAGToDAG.cpp | 155 case ISD::FCOS: in fp16SrcZerosHighBits()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 199 case ISD::FCOS: return "fcos"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 83 case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break; in SoftenFloatResult()
1227 case ISD::FCOS: ExpandFloatRes_FCOS(N, Lo, Hi); break; in ExpandFloatResult()
2259 case ISD::FCOS: in PromoteFloatResult()
2623 case ISD::FCOS: in SoftPromoteHalfResult()
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| H A D | LegalizeDAG.cpp | 2237 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3201 case ISD::FCOS: { in ExpandNode()
3210 if (Node->getOpcode() == ISD::FCOS) in ExpandNode()
4026 case ISD::FCOS: in ConvertNodeToLibcall()
4844 case ISD::FCOS: in PromoteNode()
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| H A D | LegalizeVectorOps.cpp | 369 case ISD::FCOS: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 86 case ISD::FCOS: in ScalarizeVectorResult()
1018 case ISD::FCOS: in SplitVectorResult()
3835 case ISD::FCOS: in WidenVectorResult()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 929 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
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| H A D | X86InstrFPStack.td | 754 def FCOS : I<0xD9, MRM_FF, (outs), (ins), "fcos", []>;
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1727 setOperationAction(ISD::FCOS , MVT::f128, Expand); in SparcTargetLowering()
1732 setOperationAction(ISD::FCOS , MVT::f64, Expand); in SparcTargetLowering()
1737 setOperationAction(ISD::FCOS , MVT::f32, Expand); in SparcTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 116 ISD::NodeType FPOpToExpand[] = {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in CSKYTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1590 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1636 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2, in HexagonTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 383 setOperationAction(ISD::FCOS , MVT::f64, Expand); in PPCTargetLowering()
388 setOperationAction(ISD::FCOS , MVT::f32, Expand); in PPCTargetLowering()
397 setOperationAction(ISD::FCOS , MVT::f64, Custom); in PPCTargetLowering()
403 setOperationAction(ISD::FCOS , MVT::f32, Custom); in PPCTargetLowering()
840 setOperationAction(ISD::FCOS, VT, Expand); in PPCTargetLowering()
1167 setOperationAction(ISD::FCOS, MVT::f128, Expand); in PPCTargetLowering()
11138 case ISD::FCOS: return lowerCos(Op, DAG); in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 421 setOperationAction(ISD::FCOS, MVT::f32, Expand); in MipsTargetLowering()
422 setOperationAction(ISD::FCOS, MVT::f64, Expand); in MipsTargetLowering()
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| H A D | MipsSEISelLowering.cpp | 139 setOperationAction(ISD::FCOS, MVT::f16, Promote); in MipsSETargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 124 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 366 setOperationAction(ISD::FCOS, VT, Expand); in addMVEVectorTypes()
875 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); in ARMTargetLowering()
896 setOperationAction(ISD::FCOS, MVT::v4f32, Expand); in ARMTargetLowering()
912 setOperationAction(ISD::FCOS, MVT::v2f32, Expand); in ARMTargetLowering()
1045 setOperationAction(ISD::FCOS, MVT::f64, Expand); in ARMTargetLowering()
1437 setOperationAction(ISD::FCOS, MVT::f32, Expand); in ARMTargetLowering()
1438 setOperationAction(ISD::FCOS, MVT::f64, Expand); in ARMTargetLowering()
1520 setOperationAction(ISD::FCOS, MVT::f16, Promote); in ARMTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 246 setOperationAction(ISD::FCOS, VT, Expand); in initSPUActions()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 491 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 433 setOperationAction(ISD::FCOS, MVT::f128, Expand); in AArch64TargetLowering()
579 setOperationAction(ISD::FCOS, MVT::f32, Expand); in AArch64TargetLowering()
580 setOperationAction(ISD::FCOS, MVT::f64, Expand); in AArch64TargetLowering()
591 ISD::FCOS, ISD::FSIN, ISD::FSINCOS, in AArch64TargetLowering()
1327 setOperationAction(ISD::FCOS, VT, Expand); in AArch64TargetLowering()
1465 setOperationAction(ISD::FCOS, VT, Expand); in addTypeForNEON()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 316 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, in RISCVTargetLowering()
333 ISD::FPOW, ISD::FPOWI, ISD::FCOS, ISD::FSIN, in RISCVTargetLowering()
670 setOperationAction(ISD::FCOS, VT, Expand); in RISCVTargetLowering()
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