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Searched refs:FCOPYSIGN (Results 1 – 25 of 31) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h492 FCOPYSIGN, enumerator
H A DBasicTTIImpl.h1727 ISD = ISD::FCOPYSIGN; in getTypeBasedIntrinsicInstrCost()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp81 case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N); break; in SoftenFloatResult()
860 case ISD::FCOPYSIGN: Res = SoftenFloatOp_FCOPYSIGN(N); break; in SoftenFloatOperand()
1114 return DAG.getNode(ISD::FCOPYSIGN, dl, LVT, LHS, RHS); in SoftenFloatOp_FCOPYSIGN()
1225 case ISD::FCOPYSIGN: ExpandFloatRes_FCOPYSIGN(N, Lo, Hi); break; in ExpandFloatResult()
1794 case ISD::FCOPYSIGN: Res = ExpandFloatOp_FCOPYSIGN(N); break; in ExpandFloatOperand()
1893 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), in ExpandFloatOp_FCOPYSIGN()
2111 case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo); break; in PromoteFloatOperand()
2253 case ISD::FCOPYSIGN: R = PromoteFloatRes_FCOPYSIGN(N); break; in PromoteFloatResult()
2615 case ISD::FCOPYSIGN: R = SoftPromoteHalfRes_FCOPYSIGN(N); break; in SoftPromoteHalfResult()
2907 case ISD::FCOPYSIGN: Res = SoftPromoteHalfOp_FCOPYSIGN(N, OpNo); break; in SoftPromoteHalfOperand()
H A DSelectionDAGDumper.cpp270 case ISD::FCOPYSIGN: return "fcopysign"; in getOperationName()
H A DLegalizeVectorTypes.cpp118 case ISD::FCOPYSIGN: in ScalarizeVectorResult()
961 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break; in SplitVectorResult()
1459 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo); in SplitVecRes_FCOPYSIGN()
1460 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi); in SplitVecRes_FCOPYSIGN()
2703 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break; in SplitVectorOperand()
3788 case ISD::FCOPYSIGN: in WidenVectorResult()
5443 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break; in WidenVectorOperand()
H A DLegalizeDAG.cpp1673 if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) { in ExpandFABS()
1675 return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero); in ExpandFABS()
3157 case ISD::FCOPYSIGN: in ExpandNode()
4808 case ISD::FCOPYSIGN: in PromoteNode()
4819 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN); in PromoteNode()
H A DLegalizeVectorOps.cpp366 case ISD::FCOPYSIGN: in LegalizeOp()
H A DDAGCombiner.cpp1761 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); in visit()
13745 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() && in visitBITCAST()
15441 DAG.FoldConstantArithmetic(ISD::FCOPYSIGN, SDLoc(N), VT, {N0, N1})) in visitFCOPYSIGN()
15462 N0.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
15463 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0.getOperand(0), N1); in visitFCOPYSIGN()
15470 if (N1.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
15471 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1.getOperand(1)); in visitFCOPYSIGN()
15476 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1.getOperand(0)); in visitFCOPYSIGN()
15790 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse()) { in visitFP_ROUND()
15794 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, in visitFP_ROUND()
[all …]
H A DSelectionDAG.cpp4638 case ISD::FCOPYSIGN: { in isKnownNeverNaN()
5796 case ISD::FCOPYSIGN: in foldConstantFPMath()
6025 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. in getNode()
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DTargetOpcodes.def619 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does
621 /// floating point. X and the result must have the same type. FCOPYSIGN(f32,
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp588 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand); in NVPTXTargetLowering()
589 setOperationAction(ISD::FCOPYSIGN, MVT::v2f16, Expand); in NVPTXTargetLowering()
590 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in NVPTXTargetLowering()
591 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in NVPTXTargetLowering()
2199 RoundedA = DAG.getNode(ISD::FCOPYSIGN, SL, VT, RoundedA, A); in LowerFROUND64()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1746 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in SparcTargetLowering()
1747 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in SparcTargetLowering()
1748 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in SparcTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp117 ISD::FPOW, ISD::FREM, ISD::FCOPYSIGN}; in CSKYTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp686 setOperationAction(ISD::FCOPYSIGN, VT, Legal); in RISCVTargetLowering()
898 ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN, ISD::FSQRT, in RISCVTargetLowering()
963 setTargetDAGCombine({ISD::FCOPYSIGN, ISD::MGATHER, ISD::MSCATTER, in RISCVTargetLowering()
1860 Truncated = DAG.getNode(ISD::FCOPYSIGN, DL, VT, Truncated, Src); in lowerFTRUNC_FCEIL_FFLOOR()
1913 Truncated = DAG.getNode(ISD::FCOPYSIGN, DL, VT, Truncated, Src); in lowerFROUND()
3591 case ISD::FCOPYSIGN: in LowerOperation()
9098 case ISD::FCOPYSIGN: { in PerformDAGCombine()
9119 return DAG.getNode(ISD::FCOPYSIGN, DL, VT, N->getOperand(0), in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp402 ISD::VSELECT, ISD::SELECT_CC, ISD::FCOPYSIGN, ISD::VECTOR_SHUFFLE, in AMDGPUTargetLowering()
2123 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src); in LowerFRINT()
2171 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X); in LowerFROUND()
H A DR600ISelLowering.cpp163 setOperationAction(ISD::FCOPYSIGN, {MVT::f32, MVT::f64}, Expand); in R600TargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp347 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in MipsTargetLowering()
348 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); in MipsTargetLowering()
1228 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); in LowerOperation()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp846 setOperationAction({ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp432 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in AArch64TargetLowering()
583 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); in AArch64TargetLowering()
584 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in AArch64TargetLowering()
586 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom); in AArch64TargetLowering()
588 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote); in AArch64TargetLowering()
646 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand); in AArch64TargetLowering()
656 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand); in AArch64TargetLowering()
1296 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in AArch64TargetLowering()
1477 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in addTypeForNEON()
5487 case ISD::FCOPYSIGN: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp435 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal); in PPCTargetLowering()
436 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal); in PPCTargetLowering()
438 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in PPCTargetLowering()
439 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in PPCTargetLowering()
1116 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal); in PPCTargetLowering()
1117 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal); in PPCTargetLowering()
1253 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in PPCTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp238 for (auto Op : {ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, in WebAssemblyTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp245 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in initSPUActions()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td510 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp561 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in X86TargetLowering()
615 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in X86TargetLowering()
692 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in X86TargetLowering()
693 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in X86TargetLowering()
714 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in X86TargetLowering()
769 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); in X86TargetLowering()
838 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom); in X86TargetLowering()
899 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in X86TargetLowering()
1677 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in X86TargetLowering()
23176 SDValue Adder = DAG.getNode(ISD::FCOPYSIGN, dl, VT, in LowerFROUND()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp866 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); in ARMTargetLowering()
1039 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in ARMTargetLowering()
1445 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); in ARMTargetLowering()
1446 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in ARMTargetLowering()
1518 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand); in ARMTargetLowering()
10362 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); in LowerOperation()

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