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Searched refs:ExtOpc (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp870 switch (ExtOpc) { in getRegOffOpcode()
883 switch (ExtOpc) { in getRegOffOpcode()
957 return ExtOpc; in getRegOffOpcode()
967 switch (ExtOpc) { in getDirectRegReplacement()
1608 unsigned ExtOpc = MI.getOpcode(); in replaceInstrExact() local
1635 if (ExtOpc == Hexagon::C2_cmpgei || ExtOpc == Hexagon::C2_cmpgeui) { in replaceInstrExact()
1726 unsigned ExtOpc = MI.getOpcode(); in replaceInstrExpr() local
1728 if (ExtOpc == Hexagon::A2_tfrsi) { in replaceInstrExpr()
1773 if (ExtOpc == Hexagon::A2_addi || ExtOpc == Hexagon::A2_subri) { in replaceInstrExpr()
1791 if (ExtOpc == Hexagon::M2_accii || ExtOpc == Hexagon::M2_naccii || in replaceInstrExpr()
[all …]
H A DHexagonBitSimplify.cpp2542 unsigned ExtOpc = 0; in simplifyExtractLow() local
2545 ExtOpc = Signed ? Hexagon::A2_sxtb : Hexagon::A2_zxtb; in simplifyExtractLow()
2547 ExtOpc = Signed ? Hexagon::A2_sxth : Hexagon::A2_zxth; in simplifyExtractLow()
2549 ExtOpc = Hexagon::A2_andir; in simplifyExtractLow()
2551 if (ExtOpc == 0) { in simplifyExtractLow()
2552 ExtOpc = in simplifyExtractLow()
2564 if (!validateReg({R,SR}, ExtOpc, 1)) in simplifyExtractLow()
2568 if (MI->getOpcode() == ExtOpc) { in simplifyExtractLow()
2580 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR) in simplifyExtractLow()
2582 switch (ExtOpc) { in simplifyExtractLow()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp493 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc, in buildExtOrTrunc() argument
496 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc || in buildExtOrTrunc()
497 TargetOpcode::G_SEXT == ExtOpc) && in buildExtOrTrunc()
507 Opcode = ExtOpc; in buildExtOrTrunc()
H A DLegalizerHelper.cpp2109 unsigned ExtOpc = MI.getOpcode() == TargetOpcode::G_CTTZ || in widenScalar() local
2113 auto MIBSrc = MIRBuilder.buildInstr(ExtOpc, {WideTy}, {SrcReg}); in widenScalar()
2379 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( in widenScalar() local
2381 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || in widenScalar()
2382 ExtOpc == TargetOpcode::G_ANYEXT) && in widenScalar()
2385 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) in widenScalar()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp343 unsigned ExtOpc = ISD::ANY_EXTEND) { in customLegalizeToWOp() argument
346 SDValue NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOp()
347 SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1)); in customLegalizeToWOp()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2461 unsigned ExtOpc = in lowerScalarSplat() local
2463 Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar); in lowerScalarSplat()
4687 unsigned ExtOpc = in lowerVectorIntrinsicScalars() local
4689 ScalarOp = DAG.getNode(ExtOpc, DL, XLenVT, ScalarOp); in lowerVectorIntrinsicScalars()
7020 unsigned ExtOpc = ISD::ANY_EXTEND; in ReplaceNodeResults() local
7025 Results.push_back(customLegalizeToWOp(N, DAG, ExtOpc)); in ReplaceNodeResults()
8291 unsigned ExtOpc = Op1.getOpcode(); in combineADDSUB_VLToVWADDSUB_VL() local
8298 if (ExtOpc == RISCVISD::VSEXT_VL) in combineADDSUB_VLToVWADDSUB_VL()
8343 unsigned ExtOpc = Op0.getOpcode(); in combineVWADD_W_VL_VWSUB_W_VL() local
8472 Op0 = DAG.getNode(ExtOpc, DL, NarrowVT, Op0, Mask, VL); in combineMUL_VLToVWMUL_VL()
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/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp2632 Instruction::CastOps ExtOpc = Instruction::CastOps::CastOpsEnd; in visitCallInst() local
2634 ExtOpc = cast<CastInst>(Arg)->getOpcode(); in visitCallInst()
2636 (ExtOpc == Instruction::CastOps::ZExt)) in visitCallInst()
2640 Res = Builder.CreateCast(ExtOpc, Res, II->getType()); in visitCallInst()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp1903 unsigned ExtOpc, in extendLow32IntoHigh32() argument
1906 if (ExtOpc == AMDGPU::G_ZEXT) { in extendLow32IntoHigh32()
1908 } else if (ExtOpc == AMDGPU::G_SEXT) { in extendLow32IntoHigh32()
1920 assert(ExtOpc == AMDGPU::G_ANYEXT && "not an integer extension"); in extendLow32IntoHigh32()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h746 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1299 unsigned ExtOpc = in PromoteOperand() local
1301 return DAG.getNode(ExtOpc, DL, PVT, Op); in PromoteOperand()
11406 unsigned ExtOpc, in ExtendUsesToFormExtLoad() argument
11419 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
11421 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
11743 ISD::NodeType ExtOpc) { in tryToFoldExtOfLoad() argument
11757 DoXform = ExtendUsesToFormExtLoad(VT, N, N0, ExtOpc, SetCCs, TLI); in tryToFoldExtOfLoad()
11767 Combiner.ExtendSetCCUses(SetCCs, N0, ExtLoad, ExtOpc); in tryToFoldExtOfLoad()
11786 ISD::NodeType ExtOpc) { in tryToFoldExtOfMaskedLoad() argument
11801 SDValue PassThru = DAG.getNode(ExtOpc, dl, VT, Ld->getPassThru()); in tryToFoldExtOfMaskedLoad()
H A DLegalizeIntegerTypes.cpp5321 unsigned ExtOpc = ISD::ANY_EXTEND; in PromoteIntRes_BUILD_VECTOR() local
5326 ExtOpc = NOutExtOpc; in PromoteIntRes_BUILD_VECTOR()
5327 Op = DAG.getNode(ExtOpc, dl, NOutVTElem, Op); in PromoteIntRes_BUILD_VECTOR()
H A DTargetLowering.cpp5178 ISD::NodeType ExtOpc = in LowerAsmOperandForConstraint() local
5181 ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue() : C->getSExtValue(); in LowerAsmOperandForConstraint()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp21862 Lo = DAG.getNode(ExtOpc, dl, MVT::v8i16, Lo); in SplitAndExtendv16i1()
21863 Hi = DAG.getNode(ExtOpc, dl, MVT::v8i16, Hi); in SplitAndExtendv16i1()
25463 unsigned ExtOpc = in LowerEXTEND_VECTOR_INREG() local
25466 return DAG.getNode(ExtOpc, dl, VT, In); in LowerEXTEND_VECTOR_INREG()
30132 R = DAG.getNode(ExtOpc, dl, ExtVT, R); in LowerShift()
46541 unsigned ExtOpc = LHS.getOpcode(); in combineShiftToPMULH() local
46542 if ((ExtOpc != ISD::SIGN_EXTEND && ExtOpc != ISD::ZERO_EXTEND) || in combineShiftToPMULH()
46543 RHS.getOpcode() != ExtOpc) in combineShiftToPMULH()
46559 return DAG.getNode(ExtOpc, DL, VT, Mulh); in combineShiftToPMULH()
46974 if (N0.getOpcode() == ExtOpc && in combineVectorPack()
[all …]
H A DX86TargetTransformInfo.cpp2596 unsigned ExtOpc = in getCastInstrCost() local
2602 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); in getCastInstrCost()