Lines Matching refs:ExtOpc
2461 unsigned ExtOpc = in lowerScalarSplat() local
2463 Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar); in lowerScalarSplat()
4687 unsigned ExtOpc = in lowerVectorIntrinsicScalars() local
4689 ScalarOp = DAG.getNode(ExtOpc, DL, XLenVT, ScalarOp); in lowerVectorIntrinsicScalars()
6812 unsigned ExtOpc = ISD::ANY_EXTEND) { in customLegalizeToWOp() argument
6815 SDValue NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOp()
6816 SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1)); in customLegalizeToWOp()
7020 unsigned ExtOpc = ISD::ANY_EXTEND; in ReplaceNodeResults() local
7022 ExtOpc = N->getOpcode() == ISD::SDIV ? ISD::SIGN_EXTEND in ReplaceNodeResults()
7025 Results.push_back(customLegalizeToWOp(N, DAG, ExtOpc)); in ReplaceNodeResults()
8291 unsigned ExtOpc = Op1.getOpcode(); in combineADDSUB_VLToVWADDSUB_VL() local
8295 Op1 = DAG.getNode(ExtOpc, DL, NarrowVT, Op1, Mask, VL); in combineADDSUB_VLToVWADDSUB_VL()
8298 if (ExtOpc == RISCVISD::VSEXT_VL) in combineADDSUB_VLToVWADDSUB_VL()
8343 unsigned ExtOpc = Op0.getOpcode(); in combineVWADD_W_VL_VWSUB_W_VL() local
8347 Op0 = DAG.getNode(ExtOpc, DL, NarrowVT, Op0, Mask, VL); in combineVWADD_W_VL_VWSUB_W_VL()
8470 unsigned ExtOpc = IsSignExt ? RISCVISD::VSEXT_VL : RISCVISD::VZEXT_VL; in combineMUL_VLToVWMUL_VL() local
8472 Op0 = DAG.getNode(ExtOpc, DL, NarrowVT, Op0, Mask, VL); in combineMUL_VLToVWMUL_VL()
8474 ExtOpc = IsVWMULSU ? RISCVISD::VZEXT_VL : ExtOpc; in combineMUL_VLToVWMUL_VL()
8476 Op1 = DAG.getNode(ExtOpc, DL, NarrowVT, Op1, Mask, VL); in combineMUL_VLToVWMUL_VL()