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Searched refs:EXTRACT_SUBVECTOR (Results 1 – 25 of 32) sorted by relevance

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/llvm-project-15.0.7/llvm/test/TableGen/
H A Ddag-isel-subregs.td5 // CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::EXTRACT_SUBVECTOR),
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-widen-scalable-vectortype.ll11 ; scalable-vector INSERT_SUBVECTOR and EXTRACT_SUBVECTOR is not yet available.
H A Dsve-fixed-length-subvector.ll7 ; fixed_length_vector = ISD::EXTRACT_SUBVECTOR scalable_vector, 0
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dcanonicalize-vector-extract.ll5 ; scalable case, we lower to the EXTRACT_SUBVECTOR ISD node.
108 ; EXTRACT_SUBVECTOR ISD node later.
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dextract-subvector-equal-length.ll4 ; Test for ICE in SelectionDAG::computeKnownBits when visiting EXTRACT_SUBVECTOR
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1364 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); in SplitVecRes_EXTRACT_SUBVECTOR()
1367 ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, in SplitVecRes_EXTRACT_SUBVECTOR()
2656 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, Expanded, in SplitVecRes_VECTOR_SPLICE()
2659 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiVT, Expanded, in SplitVecRes_VECTOR_SPLICE()
3022 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, in SplitVecOp_EXTRACT_SUBVECTOR()
5042 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR) in isSETCCorConvertedSETCC()
5660 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Res, in WidenVecOp_Convert()
5704 ISD::EXTRACT_SUBVECTOR, dl, DstVT, Res, in WidenVecOp_FP_TO_XINT_SAT()
5814 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), in WidenVecOp_EXTRACT_SUBVECTOR()
6211 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Select, in WidenVecOp_VSELECT()
[all …]
H A DDAGCombiner.cpp659 case ISD::EXTRACT_SUBVECTOR: in getStoreSource()
1786 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); in visit()
17965 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { in mergeStoresOfConstantsOrVecElts()
18139 OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR) in getStoreMergeCandidates()
20776 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InVT, In, in convertBuildVecZextToZext()
20993 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in combineConcatVectorOfExtracts()
21259 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in visitCONCAT_VECTORS()
21538 assert(N->getOpcode() == ISD::EXTRACT_SUBVECTOR && in foldExtractSubvectorFromShuffleVector()
21791 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NVT, in visitEXTRACT_SUBVECTOR()
21856 ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT, in visitEXTRACT_SUBVECTOR()
[all …]
H A DLegalizeIntegerTypes.cpp108 case ISD::EXTRACT_SUBVECTOR: in PromoteIntegerResult()
467 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp, in PromoteIntRes_BITCAST()
1402 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx); in PromoteIntRes_TRUNCATE()
1671 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break; in PromoteIntegerOperand()
5196 SDValue Step1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NInVT, InOp0, in PromoteIntRes_EXTRACT_SUBVECTOR()
5200 ISD::EXTRACT_SUBVECTOR, dl, OutVT, Step1, in PromoteIntRes_EXTRACT_SUBVECTOR()
5208 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), OutVT, Ops); in PromoteIntRes_EXTRACT_SUBVECTOR()
5223 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), ExtVT, Ops); in PromoteIntRes_EXTRACT_SUBVECTOR()
5537 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1)); in PromoteIntOp_EXTRACT_SUBVECTOR()
H A DSelectionDAGDumper.cpp294 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; in getOperationName()
H A DSelectionDAG.cpp2656 case ISD::EXTRACT_SUBVECTOR: { in isSplatValue()
3057 case ISD::EXTRACT_SUBVECTOR: { in computeKnownBits()
4356 case ISD::EXTRACT_SUBVECTOR: { in ComputeNumSignBits()
4881 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR || in foldCONCAT_VECTORS()
6227 if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in getNode()
6255 case ISD::EXTRACT_SUBVECTOR: { in getNode()
10652 while (V.getOpcode() == ISD::EXTRACT_SUBVECTOR) in peekThroughExtractSubvectors()
11018 return getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Op), SubVT, Op, in matchBinOpReduction()
11073 if (Op0.getOpcode() != ISD::EXTRACT_SUBVECTOR || in matchBinOpReduction()
11074 Op1.getOpcode() != ISD::EXTRACT_SUBVECTOR || in matchBinOpReduction()
[all …]
/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DAArch64SelectionDAGTest.cpp124 auto Op = DAG->getNode(ISD::EXTRACT_SUBVECTOR, Loc, VecVT, Vec, ZeroIdx); in TEST_F()
161 auto Op = DAG->getNode(ISD::EXTRACT_SUBVECTOR, Loc, VecVT, Vec, ZeroIdx); in TEST_F()
175 auto Op = DAG->getNode(ISD::EXTRACT_SUBVECTOR, Loc, VecVT, Vec, ZeroIdx); in TEST_F()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h572 EXTRACT_SUBVECTOR, enumerator
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp5204 DAG.getNode(ISD::EXTRACT_SUBVECTOR, Dl, in LowerSTORE()
5208 DAG.getNode(ISD::EXTRACT_SUBVECTOR, Dl, in LowerSTORE()
5464 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
13934 if (Ext0.getOpcode() != ISD::EXTRACT_SUBVECTOR || in performUADDVCombine()
13935 Ext1.getOpcode() != ISD::EXTRACT_SUBVECTOR || in performUADDVCombine()
15282 if (N00->getOpcode() == ISD::EXTRACT_SUBVECTOR && in performConcatVectorsCombine()
15283 N01->getOpcode() == ISD::EXTRACT_SUBVECTOR && in performConcatVectorsCombine()
15474 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR && in tryExtendDUPToExtractHigh()
15516 if (N.getOpcode() != ISD::EXTRACT_SUBVECTOR) in isEssentiallyExtractHighSubvector()
19548 case ISD::EXTRACT_SUBVECTOR: in PerformDAGCombine()
[all …]
H A DAArch64ISelDAGToDAG.cpp166 if (N->getOpcode() != ISD::EXTRACT_SUBVECTOR || in SelectExtractHigh()
693 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR) in checkHighLaneIndex()
2153 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR) in tryHighFPExt()
3590 case ISD::EXTRACT_SUBVECTOR: { in Select()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVECustomDAG.cpp254 case ISD::EXTRACT_SUBVECTOR: in getIdiomaticVectorType()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvec_extract-avx.ll7 ; an EXTRACT_SUBVECTOR node internally rather than a bunch of
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2331 ISD::EXTRACT_SUBVECTOR, in X86TargetLowering()
6357 if (LHS.getOpcode() != ISD::EXTRACT_SUBVECTOR || in getSplitVectorSrc()
6358 RHS.getOpcode() != ISD::EXTRACT_SUBVECTOR || in getSplitVectorSrc()
6983 if (V.getOpcode() == ISD::EXTRACT_SUBVECTOR && in IsNOT()
7426 if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in getTargetConstantBitsFromNode()
8295 if (Sub.getOpcode() == ISD::EXTRACT_SUBVECTOR && in getFauxShuffleMask()
8778 if (Opcode == ISD::EXTRACT_SUBVECTOR) { in getShuffleScalarElt()
14405 N0.getOpcode() != ISD::EXTRACT_SUBVECTOR || in lowerShuffleOfExtractsAsVperm()
14406 N1.getOpcode() != ISD::EXTRACT_SUBVECTOR || in lowerShuffleOfExtractsAsVperm()
14493 case ISD::EXTRACT_SUBVECTOR: { in lowerShuffleAsBroadcast()
[all …]
H A DX86ISelLowering.h1167 Op.getOpcode() == ISD::EXTRACT_SUBVECTOR || in isTargetCanonicalConstantNode()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp105 setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom); in initializeHVXLowering()
200 setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom); in initializeHVXLowering()
347 setOperationAction(ISD::EXTRACT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
2300 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RetTy, in WidenHvxSetCC()
2382 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResTy, in WidenHvxTruncate()
2449 case ISD::EXTRACT_SUBVECTOR: return LowerHvxExtractSubvector(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1645 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1694 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
3202 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp493 ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, in RISCVTargetLowering()
603 {ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, in RISCVTargetLowering()
1733 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V, Zero); in convertFromScalableVector()
2151 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Vec, in lowerBUILD_VECTOR()
2740 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1, in lowerVECTOR_SHUFFLE()
2742 V2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V2, in lowerVECTOR_SHUFFLE()
3458 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
5599 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ExtSubVecVT, Vec, in lowerEXTRACT_SUBVECTOR()
5656 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InterSubVT, Vec, in lowerEXTRACT_SUBVECTOR()
5674 Slidedown = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, Slidedown, in lowerEXTRACT_SUBVECTOR()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp169 ISD::EXTRACT_SUBVECTOR}); in WebAssemblyTargetLowering()
2468 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR) in performVectorExtendCombine()
2648 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResultVT, Vec, VecIdx); in extractSubVector()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp186 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in addTypeForNEON()
442 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addMVEVectorTypes()
6183 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast, in CombineVMOVDRRCandidateWithVecOp()
9627 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
9629 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
9631 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
9633 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
9664 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
9666 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerUDIV()
10004 Pred = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MemVT, Pred, in LowerPredicateLoad()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp318 ISD::EXTRACT_SUBVECTOR, in AMDGPUTargetLowering()
1152 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
1426 SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N, in splitVector()
1429 HiVT.isVector() ? ISD::EXTRACT_SUBVECTOR : ISD::EXTRACT_VECTOR_ELT, DL, in splitVector()
1522 {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad, in WidenOrSplitVectorLoad()
H A DSIISelLowering.cpp255 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
524 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
1601 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
1690 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val, in convertArgType()
5870 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, in lowerVECTOR_SHUFFLE()
6229 Data = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MaskPopVT, in constructRetValue()
6698 auto Subvector = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, WidenedOp, in lowerSBuffer()
7886 auto Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, NewOp, in getMemIntrinsicNode()
10105 case ISD::EXTRACT_SUBVECTOR: { in isCanonicalized()

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