Searched refs:DemandedLHS (Results 1 – 7 of 7) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 1514 APInt DemandedLHS(DemandedElts), DemandedRHS(DemandedElts); in SimplifyDemandedVectorElts() local 1526 DemandedLHS.clearBit(i); in SimplifyDemandedVectorElts() 1532 simplifyAndSetOp(I, 1, DemandedLHS, UndefElts2); in SimplifyDemandedVectorElts()
|
| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 168 APInt &DemandedLHS, APInt &DemandedRHS) { in getShuffleDemandedElts() argument 177 DemandedLHS = DemandedRHS = APInt::getZero(NumElts); in getShuffleDemandedElts() 182 DemandedLHS.setBit(0); in getShuffleDemandedElts() 196 DemandedLHS.setBit(M % NumElts); in getShuffleDemandedElts() 1777 APInt DemandedLHS, DemandedRHS; in computeKnownBitsFromOperator() local 1778 if (!getShuffleDemandedElts(Shuf, DemandedElts, DemandedLHS, DemandedRHS)) { in computeKnownBitsFromOperator() 1784 if (!!DemandedLHS) { in computeKnownBitsFromOperator() 1786 computeKnownBits(LHS, DemandedLHS, Known, Depth + 1, Q); in computeKnownBitsFromOperator() 3323 APInt DemandedLHS, DemandedRHS; in ComputeNumSignBitsImpl() local 3329 if (!!DemandedLHS) { in ComputeNumSignBitsImpl() [all …]
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 2620 APInt DemandedLHS = APInt::getNullValue(NumElts); in isSplatValue() local 2632 DemandedLHS.setBit(M); in isSplatValue() 2639 if ((DemandedLHS.isZero() && DemandedRHS.isZero()) || in isSplatValue() 2640 (!DemandedLHS.isZero() && !DemandedRHS.isZero())) in isSplatValue() 2652 if (!DemandedLHS.isZero()) in isSplatValue() 2653 return CheckSplatSrc(V.getOperand(0), DemandedLHS); in isSplatValue() 2987 DemandedLHS.clearAllBits(); in computeKnownBits() 2993 DemandedLHS.setBit((unsigned)M % NumElts); in computeKnownBits() 2998 if (!!DemandedLHS) { in computeKnownBits() 3994 DemandedLHS.setBit((unsigned)M % NumElts); in ComputeNumSignBits() [all …]
|
| H A D | TargetLowering.cpp | 1292 APInt DemandedLHS(NumElts, 0); in SimplifyDemandedBits() local 1301 DemandedLHS.clearAllBits(); in SimplifyDemandedBits() 1307 DemandedLHS.setBit(M); in SimplifyDemandedBits() 1312 if (!!DemandedLHS || !!DemandedRHS) { in SimplifyDemandedBits() 1318 if (!!DemandedLHS) { in SimplifyDemandedBits() 1319 if (SimplifyDemandedBits(Op0, DemandedBits, DemandedLHS, Known2, TLO, in SimplifyDemandedBits() 1333 Op0, DemandedBits, DemandedLHS, TLO.DAG, Depth + 1); in SimplifyDemandedBits() 3154 APInt DemandedLHS(DemandedElts); in SimplifyDemandedVectorElts() local 3182 APInt DemandedLHS(NumElts, 0); in SimplifyDemandedVectorElts() local 3190 DemandedLHS.setBit(M); in SimplifyDemandedVectorElts() [all …]
|
| H A D | DAGCombiner.cpp | 22713 APInt DemandedLHS = APInt::getNullValue(NumElts); in visitVECTOR_SHUFFLE() local 22722 APInt &Demanded = M < (int)NumElts ? DemandedLHS : DemandedRHS; in visitVECTOR_SHUFFLE() 22728 (!DemandedLHS.isNullValue() || !DemandedRHS.isNullValue()) && in visitVECTOR_SHUFFLE() 22729 (DemandedLHS.isNullValue() || in visitVECTOR_SHUFFLE() 22730 DAG.MaskedVectorIsZero(N0, DemandedLHS)) && in visitVECTOR_SHUFFLE()
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2792 SDValue DemandedLHS = TLI.SimplifyMultipleUseDemandedBits(LHS, Demanded, DAG); in simplifyMul24() local 2794 if (DemandedLHS || DemandedRHS) in simplifyMul24() 2796 DemandedLHS ? DemandedLHS : LHS, in simplifyMul24()
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 7582 DemandedLHS.setBit(InnerIdx); in getPackDemandedElts() 7597 DemandedLHS = APInt::getZero(NumElts); in getHorizDemandedElts() 36824 APInt DemandedLHS, DemandedRHS; in computeKnownBitsForTargetNode() local 36831 if (!!DemandedLHS) { in computeKnownBitsForTargetNode() 37102 APInt DemandedLHS, DemandedRHS; in ComputeNumSignBitsForTargetNode() local 37108 if (!!DemandedLHS) in ComputeNumSignBitsForTargetNode() 41204 APInt DemandedLHS, DemandedRHS; in SimplifyDemandedVectorEltsForTargetNode() local 41241 APInt DemandedLHS, DemandedRHS; in SimplifyDemandedVectorEltsForTargetNode() local 41666 if (DemandedLHS || DemandedRHS) { in SimplifyDemandedBitsForTargetNode() 41667 DemandedLHS = DemandedLHS ? DemandedLHS : LHS; in SimplifyDemandedBitsForTargetNode() [all …]
|