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Searched refs:DemandedElts (Results 1 – 25 of 59) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp64 APInt DemandedElts = in getKnownBits() local
66 return getKnownBits(R, DemandedElts); in getKnownBits()
75 computeKnownBitsImpl(R, Known, DemandedElts); in getKnownBits()
174 if (!DemandedElts) in computeKnownBitsImpl()
188 if (!DemandedElts[i]) in computeKnownBitsImpl()
356 DemandedElts, Depth + 1); in computeKnownBitsImpl()
358 DemandedElts, Depth + 1); in computeKnownBitsImpl()
365 DemandedElts, Depth + 1); in computeKnownBitsImpl()
367 DemandedElts, Depth + 1); in computeKnownBitsImpl()
622 if (!DemandedElts) in computeNumSignBits()
[all …]
/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DAArch64SelectionDAGTest.cpp95 auto DemandedElts = APInt(2, 3); in TEST_F() local
108 auto DemandedElts = APInt(2, 3); in TEST_F() local
125 auto DemandedElts = APInt(3, 7); in TEST_F() local
284 APInt DemandedElts; in TEST_F() local
288 DemandedElts = APInt(16, 3); in TEST_F()
308 APInt DemandedElts; in TEST_F() local
312 DemandedElts = APInt(16, 3); in TEST_F()
328 APInt DemandedElts; in TEST_F() local
332 DemandedElts = APInt(16, 3); in TEST_F()
352 APInt DemandedElts; in TEST_F() local
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DGISelKnownBits.h39 const APInt &DemandedElts,
43 const APInt &DemandedElts, unsigned Depth = 0);
58 const APInt &DemandedElts,
61 unsigned computeNumSignBits(Register R, const APInt &DemandedElts,
67 KnownBits getKnownBits(Register R, const APInt &DemandedElts,
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp725 if (DemandedElts[i]) { in SimplifyMultipleUseDemandedBits()
1130 if (!DemandedElts[0]) in SimplifyDemandedBits()
1142 if (DemandedElts == 1) in SimplifyDemandedBits()
1180 if (!DemandedElts[Idx]) in SimplifyDemandedBits()
1295 if (!DemandedElts[i]) in SimplifyDemandedBits()
2530 if (DemandedElts[i]) { in SimplifyDemandedBits()
2818 DemandedElts.setAllBits(); in SimplifyDemandedVectorElts()
2821 if (DemandedElts == 0) { in SimplifyDemandedVectorElts()
2851 if (!DemandedElts[0]) { in SimplifyDemandedVectorElts()
2963 if (DemandedElts[i]) { in SimplifyDemandedVectorElts()
[all …]
H A DSelectionDAG.cpp2610 if (!DemandedElts[i]) in isSplatValue()
2629 if (!DemandedElts[i]) in isSplatValue()
2733 APInt DemandedElts; in isSplatValue() local
2750 APInt DemandedElts; in getSplatSourceVector() local
2842 if (!DemandedElts[i]) in getValidMinimumShiftAmountConstant()
2871 if (!DemandedElts[i]) in getValidMaximumShiftAmountConstant()
2938 if (!DemandedElts) in computeKnownBits()
2950 if (!DemandedElts[i]) in computeKnownBits()
3072 if (DemandedElts != 1) in computeKnownBits()
11468 if (!DemandedElts) in getSplatValue()
[all …]
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp1201 if (DemandedElts.isAllOnes()) in SimplifyDemandedVectorElts()
1244 DemandedElts = EltMask; in SimplifyDemandedVectorElts()
1359 DemandedElts.isAllOnes()) { in SimplifyDemandedVectorElts()
1376 if (DemandedElts[i]) { in SimplifyDemandedVectorElts()
1410 if (DemandedElts[i] && i != MaskVal) { in SimplifyDemandedVectorElts()
1428 } else if (!DemandedElts[i]) { in SimplifyDemandedVectorElts()
1514 APInt DemandedLHS(DemandedElts), DemandedRHS(DemandedElts); in SimplifyDemandedVectorElts()
1553 InputDemandedElts = DemandedElts; in SimplifyDemandedVectorElts()
1560 if (DemandedElts[OutIdx]) in SimplifyDemandedVectorElts()
1568 if (DemandedElts[InIdx / Ratio]) in SimplifyDemandedVectorElts()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp1763 if (DemandedElts.isZero()) { in simplifyDemandedUseBitsIntrinsic()
1791 if (!DemandedElts[0]) { in simplifyDemandedVectorEltsIntrinsic()
1797 DemandedElts = 1; in simplifyDemandedVectorEltsIntrinsic()
1810 if (!DemandedElts[0]) { in simplifyDemandedVectorEltsIntrinsic()
1830 if (!DemandedElts[0]) { in simplifyDemandedVectorEltsIntrinsic()
1836 DemandedElts = 1; in simplifyDemandedVectorEltsIntrinsic()
1857 if (!DemandedElts[0]) { in simplifyDemandedVectorEltsIntrinsic()
1863 DemandedElts = 1; in simplifyDemandedVectorEltsIntrinsic()
1891 if (!DemandedElts[0]) { in simplifyDemandedVectorEltsIntrinsic()
1897 DemandedElts = 1; in simplifyDemandedVectorEltsIntrinsic()
[all …]
H A DX86ISelLowering.h1118 const APInt &DemandedElts,
1125 const APInt &DemandedElts,
1131 const APInt &DemandedElts,
1136 const APInt &DemandedElts,
1143 const APInt &DemandedElts,
1150 const APInt &DemandedElts,
1156 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
1159 bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts,
H A DX86TargetTransformInfo.h152 const APInt &DemandedElts,
180 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DValueTracking.cpp178 if (DemandedElts.isZero()) in getShuffleDemandedElts()
186 if (!DemandedElts[i]) in getShuffleDemandedElts()
217 APInt DemandedElts = in computeKnownBits() local
263 V, DemandedElts, Depth, in computeKnownBits()
410 APInt DemandedElts = in ComputeNumSignBits() local
1260 if (DemandedElts[i]) in computeKnownBitsFromOperator()
1969 if (!DemandedElts[i]) in computeKnownBits()
1983 if (!DemandedElts[i]) in computeKnownBits()
2462 if (!DemandedElts[i]) in isKnownNonZero()
2718 APInt DemandedElts = in isKnownNonZero() local
[all …]
H A DTargetTransformInfo.cpp321 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, in simplifyDemandedVectorEltsIntrinsic() argument
326 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3, in simplifyDemandedVectorEltsIntrinsic()
513 const APInt &DemandedElts, in getScalarizationOverhead() argument
515 return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract); in getScalarizationOverhead()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstCombineIntrinsic.cpp1087 APInt DemandedElts, in simplifyAMDGCNMemoryIntrinsicDemanded() argument
1104 const unsigned ActiveBits = DemandedElts.getActiveBits(); in simplifyAMDGCNMemoryIntrinsicDemanded()
1110 DemandedElts = (1 << ActiveBits) - 1; in simplifyAMDGCNMemoryIntrinsicDemanded()
1140 DemandedElts &= ~((1 << UnusedComponentsAtFront) - 1); in simplifyAMDGCNMemoryIntrinsicDemanded()
1157 DemandedElts &= (1 << countPopulation(DMaskVal)) - 1; in simplifyAMDGCNMemoryIntrinsicDemanded()
1164 if (!!DemandedElts[OrigLoadIdx]) in simplifyAMDGCNMemoryIntrinsicDemanded()
1174 unsigned NewNumElts = DemandedElts.countPopulation(); in simplifyAMDGCNMemoryIntrinsicDemanded()
1178 if (NewNumElts >= VWidth && DemandedElts.isMask()) { in simplifyAMDGCNMemoryIntrinsicDemanded()
1212 if (!!DemandedElts[OrigLoadIdx]) in simplifyAMDGCNMemoryIntrinsicDemanded()
1239 return simplifyAMDGCNMemoryIntrinsicDemanded(IC, II, DemandedElts); in simplifyDemandedVectorEltsIntrinsic()
[all …]
H A DAMDGPUISelLowering.h261 const APInt &DemandedElts,
265 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
271 const APInt &DemandedElts,
H A DAMDGPUTargetTransformInfo.h191 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3575 const APInt &DemandedElts,
3587 const APInt &DemandedElts, in targetShrinkDemandedConstant() argument
3612 const APInt &DemandedElts, KnownBits &Known,
3631 const APInt &DemandedElts,
3638 const APInt &DemandedElts,
3676 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
3693 const APInt &DemandedElts,
3703 const APInt &DemandedElts,
3748 SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
3767 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
[all …]
H A DSelectionDAG.h1881 const APInt &DemandedElts, unsigned Depth = 0) const;
1885 bool MaskedVectorIsZero(SDValue Op, const APInt &DemandedElts,
1905 KnownBits computeKnownBits(SDValue Op, const APInt &DemandedElts,
1943 unsigned ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
1956 unsigned ComputeMaxSignificantBits(SDValue Op, const APInt &DemandedElts,
1978 bool isGuaranteedNotToBePoison(SDValue Op, const APInt &DemandedElts,
1980 return isGuaranteedNotToBeUndefOrPoison(Op, DemandedElts,
2024 bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts,
2042 const APInt &DemandedElts) const;
2048 const APInt &DemandedElts) const;
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dextract-subvector-equal-length.ll5 ; with DemandedElts already as wide as the source vector.
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h414 const APInt &DemandedElts,
419 const APInt &DemandedElts,
423 const APInt &DemandedElts,
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonTargetTransformInfo.cpp127 VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) { in getScalarizationOverhead() argument
128 return BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, Extract); in getScalarizationOverhead()
H A DHexagonTargetTransformInfo.h108 const APInt &DemandedElts,
/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DTargetTransformInfo.h585 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
772 const APInt &DemandedElts,
1577 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
1633 const APInt &DemandedElts,
1964 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, in simplifyDemandedVectorEltsIntrinsic() argument
1969 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3, in simplifyDemandedVectorEltsIntrinsic()
2090 const APInt &DemandedElts, in getScalarizationOverhead() argument
2092 return Impl.getScalarizationOverhead(Ty, DemandedElts, Insert, Extract); in getScalarizationOverhead()
H A DValueTracking.h73 void computeKnownBits(const Value *V, const APInt &DemandedElts,
90 KnownBits computeKnownBits(const Value *V, const APInt &DemandedElts,
/llvm-project-15.0.7/llvm/include/llvm/Transforms/InstCombine/
H A DInstCombiner.h387 IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
525 SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, APInt &UndefElts,
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h113 const APInt &DemandedElts,
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.h86 const APInt &DemandedElts,

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