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Searched refs:DefReg (Results 1 – 25 of 39) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h414 UpdatedDefs.push_back(DefReg); in tryFoldUnmergeCast()
738 if (MO.getReg() == DefReg) in findValueFromDefImpl()
751 return DefReg; in findValueFromDefImpl()
790 Register DefReg = MI.getReg(DefIdx); in tryCombineUnmergeDefs() local
791 if (MRI.use_nodbg_empty(DefReg)) { in tryCombineUnmergeDefs()
805 MI.getOperand(DefIdx).setReg(DefReg); in tryCombineUnmergeDefs()
970 Register DefReg = MI.getReg(DefIdx); in tryCombineUnmergeValues() local
971 Builder.buildMerge(DefReg, Regs); in tryCombineUnmergeValues()
972 UpdatedDefs.push_back(DefReg); in tryCombineUnmergeValues()
988 if (!MRI.use_empty(DefReg)) { in tryCombineUnmergeValues()
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp247 Register DefReg = Def.getReg(); in transferUsedLanes() local
248 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
282 Register DefReg = Def.getReg(); in transferDefinedLanesStep() local
283 if (!Register::isVirtualRegister(DefReg)) in transferDefinedLanesStep()
285 unsigned DefRegIdx = Register::virtReg2Index(DefReg); in transferDefinedLanesStep()
425 Register DefReg = Def.getReg(); in determineInitialUsedLanes() local
428 if (Register::isVirtualRegister(DefReg)) { in determineInitialUsedLanes()
467 Register DefReg = Def.getReg(); in isUndefInput() local
468 if (!Register::isVirtualRegister(DefReg)) in isUndefInput()
470 unsigned DefRegIdx = Register::virtReg2Index(DefReg); in isUndefInput()
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H A DTailDuplicator.cpp352 Register DefReg = MI->getOperand(0).getReg(); in processPHI() local
357 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in processPHI()
358 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg))); in processPHI()
364 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) in processPHI()
365 addSSAUpdateEntry(DefReg, NewDef, PredBB); in processPHI()
H A DImplicitNullChecks.cpp718 unsigned DefReg = NoRegister; in insertFaultingInstr() local
720 DefReg = MI->getOperand(0).getReg(); in insertFaultingInstr()
731 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_OP), DefReg) in insertFaultingInstr()
H A DLiveVariables.cpp215 Register DefReg = MO.getReg(); in FindLastPartialDef() local
216 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
217 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true); in FindLastPartialDef()
H A DMachineCopyPropagation.cpp930 Register DefReg = CopyOperands->Destination->getReg(); in BackwardCopyPropagateBlock() local
933 if (!TRI->regsOverlap(DefReg, SrcReg)) { in BackwardCopyPropagateBlock()
934 MCRegister Def = DefReg.asMCReg(); in BackwardCopyPropagateBlock()
H A DPHIElimination.cpp202 Register DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction() local
203 if (MRI->use_nodbg_empty(DefReg)) { in runOnMachineFunction()
H A DMachineSink.cpp1667 for (auto DefReg : DefedRegsInCopy) { in getSingleLiveInSuccBB() local
1669 getSingleLiveInSuccBB(CurBB, SinkableBBs, DefReg, TRI); in getSingleLiveInSuccBB()
1702 for (unsigned DefReg : DefedRegsInCopy) in updateLiveIn() local
1703 for (MCSubRegIterator S(DefReg, TRI, true); S.isValid(); ++S) in updateLiveIn()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp468 Register DefReg = MO.getReg(); in oneUseDominatesOtherUses() local
469 if (!Register::isVirtualRegister(DefReg) || in oneUseDominatesOtherUses()
470 !MFI.isVRegStackified(DefReg)) in oneUseDominatesOtherUses()
472 assert(MRI.hasOneNonDBGUse(DefReg)); in oneUseDominatesOtherUses()
651 DefMO.setReg(DefReg); in moveAndTeeForMultiUse()
667 LIS.createAndComputeVirtRegInterval(DefReg); in moveAndTeeForMultiUse()
668 MFI.stackifyVReg(MRI, DefReg); in moveAndTeeForMultiUse()
673 DefDIs.clone(Tee, DefReg); in moveAndTeeForMultiUse()
909 Register DefReg = SubsequentDef->getReg(); in runOnMachineFunction() local
912 if (DefReg != UseReg || !MRI.hasOneUse(DefReg)) in runOnMachineFunction()
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H A DWebAssemblyCFGStackify.cpp831 Register DefReg = MI.getOperand(2).getReg(); in unstackifyVRegsUsedInSplitBB() local
834 MFI.unstackifyVReg(DefReg); in unstackifyVRegsUsedInSplitBB()
836 WebAssembly::getCopyOpcodeForRegClass(MRI.getRegClass(DefReg)); in unstackifyVRegsUsedInSplitBB()
838 .addReg(DefReg); in unstackifyVRegsUsedInSplitBB()
839 BuildMI(MBB, &MI, MI.getDebugLoc(), TII.get(CopyOpc), Reg).addReg(DefReg); in unstackifyVRegsUsedInSplitBB()
H A DWebAssemblyExplicitLocals.cpp192 for (auto DefReg : Def->defs()) { in findStartOfTree() local
193 if (!MFI.isVRegStackified(DefReg.getReg())) { in findStartOfTree()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVRedundantCopyElimination.cpp125 Register DefReg = MI->getOperand(0).getReg(); in optimizeBlock() local
128 if (SrcReg == RISCV::X0 && !MRI->isReserved(DefReg) && in optimizeBlock()
129 TargetReg == DefReg) { in optimizeBlock()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64RedundantCopyElimination.cpp382 Register DefReg = MI->getOperand(0).getReg(); in optimizeBlock() local
385 if (!MRI->isReserved(DefReg) && in optimizeBlock()
389 if (KnownReg.Reg != DefReg && in optimizeBlock()
390 !TRI->isSuperRegister(DefReg, KnownReg.Reg)) in optimizeBlock()
414 if (TRI->isSuperRegister(DefReg, KnownReg.Reg) && KnownReg.Imm < 0) in optimizeBlock()
H A DAArch64MIPeepholeOpt.cpp243 Register DefReg = MI.getOperand(0).getReg(); in visitORR() local
245 MRI->replaceRegWith(DefReg, SrcReg); in visitORR()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp510 const Register DefReg = I.getOperand(0).getReg(); in selectLoadStoreOp() local
511 LLT Ty = MRI.getType(DefReg); in selectLoadStoreOp()
548 addFullAddress(MIB, AM).addUse(DefReg); in selectLoadStoreOp()
571 LLT Ty = MRI.getType(DefReg); in selectFrameIndexOrGep()
624 LLT Ty = MRI.getType(DefReg); in selectGlobalValue()
643 LLT Ty = MRI.getType(DefReg); in selectConstant()
813 Register DefReg = SrcReg; in selectZext() local
830 .addReg(DefReg) in selectZext()
1329 MRI.setRegBank(DefReg, RegBank); in selectMergeValues()
1343 DefReg = Tmp; in selectMergeValues()
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H A DX86DomainReassignment.cpp593 Register DefReg = DefOp.getReg(); in buildClosure() local
594 if (!DefReg.isVirtual()) { in buildClosure()
598 visitRegister(C, DefReg, Domain, Worklist); in buildClosure()
H A DX86LoadValueInjectionLoadHardening.cpp371 RegisterRef DefReg = Def.Addr->getRegRef(DFG); in getGadgetGraph() local
372 for (auto UseID : L.getAllReachedUses(DefReg, Def)) { in getGadgetGraph()
377 if (DFG.getPRI().alias(RegisterRef(I.first), DefReg)) { in getGadgetGraph()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp673 Register DefReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
679 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
726 Register DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
745 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
785 Register DefReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
787 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in markSwapsForRemoval()
H A DPPCPreEmitPeephole.cpp258 Register DefReg; in addLinkerOpt() member
290 if (!BBI->readsRegister(Pair.DefReg, TRI) && in addLinkerOpt()
291 !BBI->modifiesRegister(Pair.DefReg, TRI)) in addLinkerOpt()
300 if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg && in addLinkerOpt()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp369 int DefReg = 0; in loadImmediate() local
373 DefReg = MO.getReg(); in loadImmediate()
392 if (DefReg != Reg) { in loadImmediate()
407 if (DefReg!= SpReg) { in loadImmediate()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp2200 Register DefReg = I.getOperand(0).getReg(); in earlySelect() local
2201 LLT Ty = MRI.getType(DefReg); in earlySelect()
2352 const LLT DefTy = MRI.getType(DefReg); in select()
2355 MRI.getRegClassOrRegBank(DefReg); in select()
2519 const LLT DefTy = MRI.getType(DefReg); in select()
2596 MIB.buildCopy({DefReg}, {DefGPRReg}); in select()
3195 const LLT DstTy = MRI.getType(DefReg); in select()
3292 {DefReg}, {SrcReg}) in select()
5245 const LLT DstTy = MRI.getType(DefReg); in selectUSMovFromExtend()
6009 Register DefReg = MI.getOperand(0).getReg(); in isWorthFoldingIntoExtendedReg() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp1653 Register DefReg = Def.getReg(); in tryFoldLoad() local
1655 if (DefReg.isPhysical() || !TRI->isVGPR(*MRI, DefReg)) in tryFoldLoad()
1660 for (const MachineInstr &I : MRI->use_nodbg_instructions(DefReg)) { in tryFoldLoad()
1680 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in tryFoldLoad()
1681 MRI->setRegClass(DefReg, TRI->getEquivalentAGPRClass(RC)); in tryFoldLoad()
1683 MRI->setRegClass(DefReg, RC); in tryFoldLoad()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp214 Register DefReg = MODef.getReg(); in eraseInstrWithNoUses() local
215 if (!Register::isVirtualRegister(DefReg)) { in eraseInstrWithNoUses()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp177 static bool isRegUsedByPhiNodes(Register DefReg, in isRegUsedByPhiNodes() argument
180 if (P.second == DefReg) in isRegUsedByPhiNodes()
199 Register DefReg = findLocalRegDef(LocalMI); in flushLocalValueMap() local
200 if (!DefReg) in flushLocalValueMap()
202 if (FuncInfo.RegsWithFixups.count(DefReg)) in flushLocalValueMap()
204 bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo); in flushLocalValueMap()
205 if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) { in flushLocalValueMap()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp1044 unsigned DefReg = 0; in getUniqueDefVReg() local
1051 if (DefReg != 0) in getUniqueDefVReg()
1053 DefReg = R; in getUniqueDefVReg()
1055 return DefReg; in getUniqueDefVReg()

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