265   MachineInstr *emitADD(Register DefReg, MachineOperand &LHS,
2200     Register DefReg = I.getOperand(0).getReg();  in earlySelect()  local
2201     LLT Ty = MRI.getType(DefReg);  in earlySelect()
2204       RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI);  in earlySelect()
2207       RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI);  in earlySelect()
2351       const Register DefReg = I.getOperand(0).getReg();  in select()  local
2352       const LLT DefTy = MRI.getType(DefReg);  in select()
2355         MRI.getRegClassOrRegBank(DefReg);  in select()
2374       return RBI.constrainGenericRegister(DefReg, *DefRC, MRI);  in select()
2518     const Register DefReg = I.getOperand(0).getReg();  in select()  local
2519     const LLT DefTy = MRI.getType(DefReg);  in select()
2521     const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);  in select()
2582         MIB.buildCopy({DefReg}, {LoadMI->getOperand(0).getReg()});  in select()
2584         return RBI.constrainGenericRegister(DefReg, FPRRC, MRI);  in select()
2596       MIB.buildCopy({DefReg}, {DefGPRReg});  in select()
2598       if (!RBI.constrainGenericRegister(DefReg, FPRRC, MRI)) {  in select()
2949     const Register DefReg = I.getOperand(0).getReg();  in select()  local
2950     const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);  in select()
3008     const Register DefReg = I.getOperand(0).getReg();  in select()  local
3009     const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);  in select()
3193     const Register DefReg = I.getOperand(0).getReg();  in select()  local
3195     const LLT DstTy = MRI.getType(DefReg);  in select()
3208     assert((*RBI.getRegBank(DefReg, MRI, TRI)).getID() ==  in select()
3252         MIB.buildInstr(AArch64::SUBREG_TO_REG, {DefReg}, {})  in select()
3257         if (!RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass,  in select()
3292                              {DefReg}, {SrcReg})  in select()
3297                              {DefReg}, {SrcReg})  in select()
4484 AArch64InstructionSelector::emitADD(Register DefReg, MachineOperand &LHS,  in emitADD()  argument
4493   return emitAddSub(OpcTable, DefReg, LHS, RHS, MIRBuilder);  in emitADD()
5244   const Register DefReg = MI.getOperand(0).getReg();  in selectUSMovFromExtend()  local
5245   const LLT DstTy = MRI.getType(DefReg);  in selectUSMovFromExtend()
5289     ExtI = MIB.buildInstr(AArch64::SUBREG_TO_REG, {DefReg}, {})  in selectUSMovFromExtend()
5293     RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI);  in selectUSMovFromExtend()
5295     ExtI = MIB.buildInstr(Opcode, {DefReg}, {Src0}).addImm(Lane);  in selectUSMovFromExtend()
6009   Register DefReg = MI.getOperand(0).getReg();  in isWorthFoldingIntoExtendedReg()  local
6010   if (MRI.hasOneNonDBGUse(DefReg) ||  in isWorthFoldingIntoExtendedReg()
6022   return all_of(MRI.use_nodbg_instructions(DefReg),  in isWorthFoldingIntoExtendedReg()