Home
last modified time | relevance | path

Searched refs:DefIdx (Results 1 – 25 of 44) sorted by relevance

12

/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInstrItineraries.h184 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
188 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
190 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
198 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
205 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
210 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
220 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
H A DMCSubtargetInfo.h177 unsigned DefIdx) const { in getWriteLatencyEntry() argument
178 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
181 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h542 unsigned DefIdx = 0; in getDefIndex() local
546 ++DefIdx; in getDefIndex()
549 return DefIdx; in getDefIndex()
789 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineUnmergeDefs() local
790 Register DefReg = MI.getReg(DefIdx); in tryCombineUnmergeDefs()
792 DeadDefs[DefIdx] = true; in tryCombineUnmergeDefs()
807 DeadDefs[DefIdx] = true; in tryCombineUnmergeDefs()
912 ++j, ++DefIdx) in tryCombineUnmergeValues()
964 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineUnmergeValues() local
1186 unsigned DefIdx = 0) {
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetSchedule.cpp157 unsigned DefIdx = 0; in findDefIdx() local
161 ++DefIdx; in findDefIdx()
163 return DefIdx; in findDefIdx()
217 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
218 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
221 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
243 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
H A DLiveIntervalCalc.cpp36 SlotIndex DefIdx = in createDeadDef() local
40 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
181 unsigned DefIdx; in extendToUses() local
184 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { in extendToUses()
187 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber(); in extendToUses()
H A DTargetInstrInfo.cpp1099 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1169 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1258 unsigned DefIdx, in getOperandLatency() argument
1267 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs() argument
1273 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs); in getRegSequenceInputs()
1277 assert(DefIdx == 0 && "REG_SEQUENCE only has one def"); in getRegSequenceInputs()
1294 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregInputs() argument
1300 return getExtractSubregLikeInputs(MI, DefIdx, InputReg); in getExtractSubregInputs()
1304 assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def"); in getExtractSubregInputs()
1319 const MachineInstr &MI, unsigned DefIdx, in getInsertSubregInputs() argument
[all …]
H A DPeepholeOptimizer.cpp373 unsigned DefIdx = 0; member in __anon4a9001390111::ValueTracker
427 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
1833 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1854 const MachineOperand DefOp = Def->getOperand(DefIdx); in getNextSourceFromBitcast()
1898 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromRegSequence()
1942 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromInsertSubreg()
1971 const MachineOperand &MODef = Def->getOperand(DefIdx); in getNextSourceFromInsertSubreg()
2067 assert(((Def->getOperand(DefIdx).isDef() && in getNextSourceImpl()
2068 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
2070 Def->getOperand(DefIdx).isImplicit()) && in getNextSourceImpl()
[all …]
H A DLiveRangeEdit.cpp164 SlotIndex DefIdx; in canRematerializeAt() local
166 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); in canRematerializeAt()
173 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
H A DMachineVerifier.cpp259 SlotIndex DefIdx, const LiveRange &LR,
2010 unsigned DefIdx; in visitMachineOperand() local
2014 Reg != MI->getOperand(DefIdx).getReg()) in visitMachineOperand()
2257 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) { in checkLivenessAtDef()
2259 if (VNI->def != DefIdx) { in checkLivenessAtDef()
2266 report_context(DefIdx); in checkLivenessAtDef()
2274 report_context(DefIdx); in checkLivenessAtDef()
2278 LiveQueryResult LRQ = LR.Query(DefIdx); in checkLivenessAtDef()
2434 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI); in checkLiveness() local
2435 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber()); in checkLiveness()
[all …]
H A DMachineInstr.cpp262 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand() local
263 if (DefIdx != -1) in addOperand()
264 tieOperands(DefIdx, OpNo); in addOperand()
848 unsigned DefIdx; in getRegClassConstraint() local
849 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
850 OpIdx = DefIdx; in getRegClassConstraint()
1052 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() argument
1053 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands()
1060 if (DefIdx < TiedMax) in tieOperands()
1061 UseMO.TiedTo = DefIdx + 1; in tieOperands()
H A DRenameIndependentSubregs.cpp335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); in computeMainRangesFixFlags() local
336 SlotIndex RegDefIdx = DefIdx.getRegSlot(); in computeMainRangesFixFlags()
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCSchedule.cpp43 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
44 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
47 STI.getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h61 const MachineInstr &MI, unsigned DefIdx,
74 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
90 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
319 const MachineInstr &DefMI, unsigned DefIdx,
323 SDNode *DefNode, unsigned DefIdx,
426 unsigned DefIdx, unsigned DefAlign) const;
430 unsigned DefIdx, unsigned DefAlign) const;
441 unsigned DefIdx, unsigned DefAlign,
446 const MachineInstr &DefMI, unsigned DefIdx,
463 const MachineInstr &DefMI, unsigned DefIdx,
[all …]
H A DARMBaseInstrInfo.cpp3870 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getVLDMDefCycle()
3873 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3911 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getLDMDefCycle()
3914 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
4029 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
4141 DefIdx = Idx; in getBundledDefMI()
4357 unsigned DefIdx, in getOperandLatency() argument
4364 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency()
4801 unsigned DefIdx, in hasHighOperandLatency() argument
5432 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp623 int DefIdx = SwapMap[DefMI]; in formWebs() local
624 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs()
628 SwapVector[DefIdx].VSEId, in formWebs()
727 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
729 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
730 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
736 LLVM_DEBUG(dbgs() << " def " << DefIdx << ": "); in recordUnoptimizableWebs()
803 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
804 SwapVector[DefIdx].WillRemove = 1; in markSwapsForRemoval()
H A DPPCInstrInfo.h414 const MachineInstr &DefMI, unsigned DefIdx,
418 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
420 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
426 unsigned DefIdx) const override { in hasLowDefLatency() argument
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h532 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
550 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
570 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
1247 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
1261 unsigned DefIdx, in getExtractSubregLikeInputs() argument
1275 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs() argument
1601 SDNode *DefNode, unsigned DefIdx,
1613 const MachineInstr &DefMI, unsigned DefIdx,
1643 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
1653 unsigned DefIdx) const;
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.cpp474 unsigned DefIdx = N->getOperand(i).getResNo(); in AddSchedEdges() local
510 ST.adjustSchedDependency(OpSU, DefIdx, &SU, i, Dep); in AddSchedEdges()
573 DefIdx = 0; in InitNodeNumDefs()
587 for (;DefIdx < NodeNumDefs; ++DefIdx) { in Advance()
588 if (!Node->hasAnyUseOfValue(DefIdx)) in Advance()
590 ValueType = Node->getSimpleValueType(DefIdx); in Advance()
591 ++DefIdx; in Advance()
653 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
657 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
H A DScheduleDAGSDNodes.h141 unsigned DefIdx = 0; variable
160 return DefIdx-1; in GetIdx()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp403 int DefIdx = mapRegToGPRIndex(MI.getOperand(0).getReg()); in handleADRP() local
406 if (DefIdx != OpIdx && (DefInfo.OneUser || DefInfo.MultiUsers)) in handleADRP()
571 int DefIdx = mapRegToGPRIndex(Def.getReg()); in runOnMachineFunction() local
573 if (DefIdx >= 0 && OpIdx >= 0 && in runOnMachineFunction()
574 handleMiddleInst(MI, LOHInfos[DefIdx], LOHInfos[OpIdx])) in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp217 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in getLatency() local
218 DefIdx != DefEnd; ++DefIdx) { in getLatency()
221 DefIdx); in getLatency()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp203 unsigned DefIdx = 0; in tryInlineAsm() local
207 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx)) in tryInlineAsm()
208 IsTiedToChangedOp = OpChanged[DefIdx]; in tryInlineAsm()
294 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx); in tryInlineAsm()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp158 unsigned DefIdx = 0; in selectInlineAsm() local
162 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx)) in selectInlineAsm()
163 IsTiedToChangedOp = OpChanged[DefIdx]; in selectInlineAsm()
248 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx); in selectInlineAsm()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp576 int DefIdx = -1; in restoreLatency() local
588 DefIdx = OpNum; in restoreLatency()
591 assert(DefIdx >= 0 && "Def Reg not found in Src MI"); in restoreLatency()
598 DefIdx, *DstI, OpNum)); in restoreLatency()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp435 unsigned DefIdx = OpInfo.getMatchedOperand(); in lowerInlineAsm() local
438 for (unsigned i = 0; i < DefIdx; ++i) in lowerInlineAsm()
472 unsigned Flag = InlineAsm::getFlagWordForMatchingOp(UseFlag, DefIdx); in lowerInlineAsm()

12