1089                                    SDNode *DefNode, unsigned DefIdx,  in getOperandLatency()  argument
1099     return ItinData->getOperandCycle(DefClass, DefIdx);  in getOperandLatency()
1101   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1163                                        unsigned DefIdx) const {  in hasLowDefLatency()
1169   int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in hasLowDefLatency()
1258                                        unsigned DefIdx,  in getOperandLatency()  argument
1263   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1267     const MachineInstr &MI, unsigned DefIdx,  in getRegSequenceInputs()  argument
1273     return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);  in getRegSequenceInputs()
1277   assert(DefIdx == 0 && "REG_SEQUENCE only has one def");  in getRegSequenceInputs()
1294     const MachineInstr &MI, unsigned DefIdx,  in getExtractSubregInputs()  argument
1300     return getExtractSubregLikeInputs(MI, DefIdx, InputReg);  in getExtractSubregInputs()
1304   assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");  in getExtractSubregInputs()
1319     const MachineInstr &MI, unsigned DefIdx,  in getInsertSubregInputs()  argument
1325     return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);  in getInsertSubregInputs()
1329   assert(DefIdx == 0 && "INSERT_SUBREG only has one def");  in getInsertSubregInputs()