| /llvm-project-15.0.7/clang/test/CXX/temp/temp.spec/temp.explicit/ |
| H A D | p1-emit.cpp | 22 long& get(bool Cond1, bool Cond2) { in get() argument
26 return Cond1? X<long>::member1 in get()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | GuardWidening.cpp | 190 bool widenCondCommon(Value *Cond0, Value *Cond1, Instruction *InsertPt,
252 bool isWideningCondProfitable(Value *Cond0, Value *Cond1, bool InvertCond) { in isWideningCondProfitable() argument
254 return widenCondCommon(Cond0, Cond1, /*InsertPt=*/nullptr, ResultUnused, in isWideningCondProfitable()
502 bool GuardWideningImpl::widenCondCommon(Value *Cond0, Value *Cond1, in widenCondCommon() argument
513 match(Cond1, m_ICmp(Pred1, m_Specific(LHS), m_ConstantInt(RHS1)))) { in widenCondCommon()
544 parseRangeChecks(Cond0, Checks) && parseRangeChecks(Cond1, Checks) && in widenCondCommon()
567 makeAvailableAt(Cond1, InsertPt); in widenCondCommon()
569 Cond1 = BinaryOperator::CreateNot(Cond1, "inverted", InsertPt); in widenCondCommon()
570 Result = BinaryOperator::CreateAnd(Cond0, Cond1, "wide.chk", InsertPt); in widenCondCommon()
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | select_fmf.ll | 6 ; select Cond0, (select Cond1, X, Y), Y -> select (and Cond0, Cond1), X, Y
64 ; select Cond0, X, (select Cond1, X, Y) -> select (or Cond0, Cond1), X, Y
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| /llvm-project-15.0.7/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | IdenticalExprChecker.cpp | 136 const Expr *Cond1 = I->getCond(); in VisitIfStmt() local
140 if (isIdenticalStmt(AC->getASTContext(), Cond1, Cond2, false)) { in VisitIfStmt()
141 SourceRange Sr = Cond1->getSourceRange(); in VisitIfStmt()
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Utils/ |
| H A D | LibCallsShrinkWrap.cpp | 107 auto Cond1 = createCond(BBBuilder, Arg, Cmp, Val); in createOrCond() local
108 return BBBuilder.CreateOr(Cond1, Cond2); in createOrCond()
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Coroutines/ |
| H A D | CoroSplit.cpp | 1295 auto *Cond1 = dyn_cast<ConstantInt>(CondCmp->getOperand(1)); in simplifyTerminatorLeadingToRet() local
1296 if (!Cond0 || !Cond1) in simplifyTerminatorLeadingToRet()
1303 CondCmp->getPredicate(), Cond0, Cond1, DL)); in simplifyTerminatorLeadingToRet()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | IfConversion.cpp | 1798 SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond; in IfConvertDiamondCommon() local
1812 std::swap(Cond1, Cond2); in IfConvertDiamondCommon()
1978 PredicateBlock(*BBI1, MBB1.end(), *Cond1, &RedefsByFalse); in IfConvertDiamondCommon()
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| H A D | ModuloSchedule.cpp | 324 SmallVector<MachineOperand, 4> Cond1; in generateEpilog() local
325 TII->insertBranch(*LastEpilogBB, LoopExitBB, nullptr, Cond1, DebugLoc()); in generateEpilog()
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| H A D | CodeGenPrepare.cpp | 8276 Value *Cond1, *Cond2; in splitBranchCondition() local
8278 m_LogicalAnd(m_OneUse(m_Value(Cond1)), m_OneUse(m_Value(Cond2))))) in splitBranchCondition()
8280 else if (match(LogicOp, m_LogicalOr(m_OneUse(m_Value(Cond1)), in splitBranchCondition()
8292 if (!IsGoodCond(Cond1) || !IsGoodCond(Cond2)) in splitBranchCondition()
8304 Br1->setCondition(Cond1); in splitBranchCondition()
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | IRBuilder.h | 1548 Value *CreateLogicalAnd(Value *Cond1, Value *Cond2, const Twine &Name = "") {
1550 return CreateSelect(Cond1, Cond2,
1554 Value *CreateLogicalOr(Value *Cond1, Value *Cond2, const Twine &Name = "") {
1556 return CreateSelect(Cond1, ConstantInt::getAllOnesValue(Cond2->getType()),
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 5241 SDValue Cond1 = N->getOperand(0); in WidenVecRes_Select() local
5242 EVT CondVT = Cond1.getValueType(); in WidenVecRes_Select()
5255 Cond1 = GetWidenedVector(Cond1); in WidenVecRes_Select()
5268 if (Cond1.getValueType() != CondWidenVT) in WidenVecRes_Select()
5269 Cond1 = ModifyToType(Cond1, CondWidenVT); in WidenVecRes_Select()
5276 return DAG.getNode(Opcode, SDLoc(N), WidenVT, Cond1, InOp1, InOp2, in WidenVecRes_Select()
5278 return DAG.getNode(Opcode, SDLoc(N), WidenVT, Cond1, InOp1, InOp2); in WidenVecRes_Select()
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| H A D | DAGCombiner.cpp | 10293 SDValue Cond1 = N0.getOperand(1); in foldVSelectToSignBitSplatMask() local
10300 if (CC == ISD::SETLT && isNullOrNullSplat(Cond1)) in foldVSelectToSignBitSplatMask()
10302 else if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(Cond1)) in foldVSelectToSignBitSplatMask()
10379 SDValue Cond1 = N0->getOperand(1); in visitSELECT() local
10381 DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond1, N1, N2, Flags); in visitSELECT()
10392 SDValue Cond1 = N0->getOperand(1); in visitSELECT() local
10394 Cond1, N1, N2, Flags); in visitSELECT()
10451 SDValue Cond0 = N0.getOperand(0), Cond1 = N0.getOperand(1); in visitSELECT() local
10459 if (SDValue FMinMax = combineMinNumMaxNum(DL, VT, Cond0, Cond1, N1, N2, in visitSELECT()
10472 auto *NotC = dyn_cast<ConstantSDNode>(Cond1); in visitSELECT()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 44827 SDValue Cond1 = Cond.getOperand(1); in combineSelect() local
44849 if (LHS == Cond0 && RHS == Cond1) { in combineSelect()
44853 Cond = DAG.getSetCC(SDLoc(Cond), CondVT, Cond0, Cond1, NewCC); in combineSelect()
44858 Cond = DAG.getSetCC(SDLoc(Cond), CondVT, Cond0, Cond1, NewCC); in combineSelect()
44877 Cond1 == InnerSetCC.getOperand(1)) { in combineSelect()
44887 Cond = DAG.getSetCC(DL, CondVT, Cond0, Cond1, NewCC); in combineSelect()
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