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Searched refs:Cond (Results 1 – 25 of 412) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DLoopBoundSplit.cpp53 Cond.ICmp = ICmp; in analyzeICmp()
54 if (match(ICmp, m_ICmp(Cond.Pred, m_Value(Cond.AddRecValue), in analyzeICmp()
62 std::swap(Cond.AddRecValue, Cond.BoundValue); in analyzeICmp()
64 Cond.Pred = ICmpInst::getSwappedPredicate(Cond.Pred); in analyzeICmp()
69 Cond.NonPHIAddRecValue = Cond.AddRecValue; in analyzeICmp()
73 if (Cond.AddRecSCEV && isa<PHINode>(Cond.AddRecValue)) { in analyzeICmp()
92 if (Cond.Pred == ICmpInst::ICMP_SLT || Cond.Pred == ICmpInst::ICMP_ULT) in calculateUpperBound()
98 if (Cond.Pred != ICmpInst::ICMP_ULE && Cond.Pred != ICmpInst::ICMP_SLE) in calculateUpperBound()
115 Cond.Pred = Pred; in calculateUpperBound()
219 Cond.BI = ExitingBI; in canSplitLoopBound()
[all …]
/llvm-project-15.0.7/clang-tools-extra/clang-tidy/bugprone/
H A DInfiniteLoopCheck.cpp49 if (const auto *DRE = dyn_cast<DeclRefExpr>(Cond)) { in isVarThatIsPossiblyChanged()
68 } else if (const auto *CE = dyn_cast<CastExpr>(Cond)) { in isVarThatIsPossiblyChanged()
90 for (const Stmt *Child : Cond->children()) { in isAtLeastOneCondVarChanged()
101 static std::string getCondVarNames(const Stmt *Cond) { in getCondVarNames() argument
102 if (const auto *DRE = dyn_cast<DeclRefExpr>(Cond)) { in getCondVarNames()
108 for (const Stmt *Child : Cond->children()) { in getCondVarNames()
122 if (Cond.isValueDependent()) { in isKnownToHaveValue()
144 if (Cond.EvaluateAsBooleanCondition(Result, Ctx)) in isKnownToHaveValue()
167 if (isKnownToHaveValue(*Cond, *Result.Context, false)) in check()
175 Cond = Init; in check()
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/llvm-project-15.0.7/clang/lib/StaticAnalyzer/Core/
H A DSimpleConstraintManager.cpp26 DefinedSVal Cond, in assumeInternal() argument
29 if (Optional<Loc> LV = Cond.getAs<Loc>()) { in assumeInternal()
41 return assume(State, Cond.castAs<NonLoc>(), Assumption); in assumeInternal()
46 State = assumeAux(State, Cond, Assumption); in assume()
48 return EE->processAssume(State, Cond, Assumption); in assume()
53 NonLoc Cond, in assumeAux() argument
58 if (!canReasonAbout(Cond)) { in assumeAux()
60 SymbolRef Sym = Cond.getAsSymbol(); in assumeAux()
65 switch (Cond.getSubKind()) { in assumeAux()
70 nonloc::SymbolVal SV = Cond.castAs<nonloc::SymbolVal>(); in assumeAux()
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/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.cpp110 Cond.push_back(MachineOperand::CreateImm(true)); in analyzeBranch()
111 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
118 Cond.push_back(MachineOperand::CreateImm(false)); in analyzeBranch()
119 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
164 if (Cond.empty()) { in insertBranch()
172 assert(Cond.size() == 2 && "Expected a flag and a successor block"); in insertBranch()
174 if (Cond[0].getImm()) in insertBranch()
175 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]); in insertBranch()
186 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
187 assert(Cond.size() == 2 && "Expected a flag and a condition expression"); in reverseBranchCondition()
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H A DWebAssemblyLowerBrUnless.cpp70 Register Cond = MI.getOperand(1).getReg(); in runOnMachineFunction() local
74 if (MFI.isVRegStackified(Cond)) { in runOnMachineFunction()
75 assert(MRI.hasOneDef(Cond)); in runOnMachineFunction()
76 MachineInstr *Def = MRI.getVRegDef(Cond); in runOnMachineFunction()
177 Cond = Def->getOperand(1).getReg(); in runOnMachineFunction()
192 .addReg(Cond); in runOnMachineFunction()
194 Cond = Tmp; in runOnMachineFunction()
203 .addReg(Cond); in runOnMachineFunction()
/llvm-project-15.0.7/clang/lib/Analysis/FlowSensitive/
H A DTypeErasedDataflowAnalysis.cpp82 auto *Cond = S->getCond(); in VisitIfStmt() local
83 assert(Cond != nullptr); in VisitIfStmt()
84 extendFlowCondition(*Cond); in VisitIfStmt()
88 auto *Cond = S->getCond(); in VisitWhileStmt() local
89 assert(Cond != nullptr); in VisitWhileStmt()
94 auto *Cond = S->getCond(); in VisitDoStmt() local
95 assert(Cond != nullptr); in VisitDoStmt()
100 auto *Cond = S->getCond(); in VisitForStmt() local
101 if (Cond != nullptr) in VisitForStmt()
113 auto *Cond = S->getCond(); in VisitConditionalOperator() local
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/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DLibCallsShrinkWrap.cpp136 Value *Cond = nullptr; in performCallDomainErrorOnly() local
181 shrinkWrapCI(CI, Cond); in performCallDomainErrorOnly()
188 Value *Cond = nullptr; in performCallRangeErrorOnly() local
206 Cond = generateTwoRangeCond(CI, Func); in performCallRangeErrorOnly()
213 Cond = generateOneRangeCond(CI, Func); in performCallRangeErrorOnly()
219 shrinkWrapCI(CI, Cond); in performCallRangeErrorOnly()
226 Value *Cond = nullptr; in performCallErrors() local
273 Cond = generateCondForPow(CI, Func); in performCallErrors()
274 if (Cond == nullptr) in performCallErrors()
282 shrinkWrapCI(CI, Cond); in performCallErrors()
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/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp133 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
134 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in reverseBranchCondition()
160 Cond[0].setImm(CC); in reverseBranchCondition()
167 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
201 Cond.clear(); in analyzeBranch()
225 if (Cond.empty()) { in analyzeBranch()
228 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
234 assert(Cond.size() == 1); in analyzeBranch()
256 ArrayRef<MachineOperand> Cond, in insertBranch() argument
261 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
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/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp220 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
221 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
241 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
242 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
279 assert((Cond.size() == 2 || Cond.size() == 0) && in insertBranch()
284 if (Cond.empty()) { in insertBranch()
290 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in insertBranch()
297 assert(Cond.size() == 2 && "Unexpected number of components!"); in insertBranch()
299 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in insertBranch()
404 assert((Cond.size() == 2) && in reverseBranchCondition()
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/llvm-project-15.0.7/libc/utils/UnitTest/
H A DLibcTest.cpp90 bool test(RunContext *Ctx, TestCondition Cond, ValType LHS, ValType RHS, in test() argument
97 switch (Cond) { in test()
210 template bool test<char>(RunContext *Ctx, TestCondition Cond, char LHS,
222 template bool test<long>(RunContext *Ctx, TestCondition Cond, long LHS,
226 template bool test<long long>(RunContext *Ctx, TestCondition Cond,
231 template bool test<unsigned char>(RunContext *Ctx, TestCondition Cond,
236 template bool test<unsigned short>(RunContext *Ctx, TestCondition Cond,
241 template bool test<unsigned int>(RunContext *Ctx, TestCondition Cond,
246 template bool test<unsigned long>(RunContext *Ctx, TestCondition Cond,
251 template bool test<bool>(RunContext *Ctx, TestCondition Cond, bool LHS,
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/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp202 if (!Cond.empty()) in analyzeBranch()
208 Cond.push_back(I->getOperand(1)); in analyzeBranch()
209 Cond.push_back(I->getOperand(2)); in analyzeBranch()
210 Cond.push_back(I->getOperand(3)); in analyzeBranch()
225 Cond.clear(); in analyzeBranch()
351 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
352 assert((Cond.size() == 3) && "Invalid ARC branch condition!"); in reverseBranchCondition()
353 Cond[2].setImm(getOppositeBranchCondition((ARCCC::CondCode)Cond[2].getImm())); in reverseBranchCondition()
379 assert((Cond.size() == 3 || Cond.size() == 0) && in insertBranch()
382 if (Cond.empty()) { in insertBranch()
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/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dvector.cpp56 __typeof__(Cond? c16 : c16) *c16p1 = &c16; in conditional()
57 __typeof__(Cond? ll16 : ll16) *ll16p1 = &ll16; in conditional()
62 __typeof__(Cond? c16 : c16e) *c16ep2 = &c16e; in conditional()
63 __typeof__(Cond? c16e : c16) *c16ep3 = &c16e; in conditional()
68 (void)(Cond? c16 : ll16); in conditional()
69 (void)(Cond? ll16e : c16e); in conditional()
70 (void)(Cond? ll16e : c16); in conditional()
221 (void)(Cond? to_c16 : to_c16e); in test_implicit_conversions()
222 (void)(Cond? to_ll16e : to_ll16); in test_implicit_conversions()
225 (void)(Cond? to_c16 : to_ll16); in test_implicit_conversions()
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/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp98 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
116 Cond.push_back(LastInst.getOperand(0)); in analyzeBranch()
134 Cond.push_back(SecondLastInst.getOperand(0)); in analyzeBranch()
183 ArrayRef<MachineOperand> Cond, in insertBranch() argument
190 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
195 if (Cond.empty()) // Unconditional branch in insertBranch()
198 BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB); in insertBranch()
203 BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB); in insertBranch()
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/readability/
H A Dsimplify-bool-expr-cxx17.cpp3 bool foo(bool Cond) { in foo() argument
6 if (RAII Object; Cond) in foo()
11 if (bool X = Cond; X) in foo()
16 if (bool X = Cond; X) in foo()
/llvm-project-15.0.7/clang/test/SemaTemplate/
H A Dvalue-dependent-null-pointer-constant.cpp7 const char *f0(bool Cond) { in f0()
8 return Cond? "honk" : N; in f0()
16 const char *f1(bool Cond) { in f1()
17 return Cond? N : "honk"; in f1()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp2098 Cond = Cond.getOperand(0); in LowerSELECT()
2170 Cond = Cond.getOperand(0); in LowerSELECT()
2174 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { in LowerSELECT()
2185 Cond = EmitTest(Cond, M68k::COND_NE, DL, DAG); in LowerSELECT()
2272 Cond = Cond.getOperand(0); in LowerBRCOND()
2283 Cond = Cond.getOperand(0); in LowerBRCOND()
2305 Cond = Cond.getNode()->getOperand(1); in LowerBRCOND()
2419 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { in LowerBRCOND()
2427 Cond = Cond.getOperand(0).getOperand(1); in LowerBRCOND()
2435 Cond = Cond.getOperand(0); in LowerBRCOND()
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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp104 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
121 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
125 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
126 assert((Cond[i].isImm() || Cond[i].isReg()) && in BuildCondBr()
128 MIB.add(Cond[i]); in BuildCondBr()
148 assert((Cond.size() <= 3) && in insertBranch()
153 BuildCondBr(MBB, TBB, DL, Cond); in insertBranch()
160 if (Cond.empty()) in insertBranch()
163 BuildCondBr(MBB, TBB, DL, Cond); in insertBranch()
197 assert( (Cond.size() && Cond.size() <= 3) && in reverseBranchCondition()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FlagsCopyLowering.cpp740 X86::CondCode Cond = X86::getCondFromSETCC(MI); in collectCondsInRegs() local
745 CondRegs[Cond] = MI.getOperand(0).getReg(); in collectCondsInRegs()
758 const DebugLoc &TestLoc, X86::CondCode Cond) { in promoteCondToReg() argument
771 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg()
798 X86::CondCode Cond = X86::COND_INVALID; in rewriteArithmetic() local
810 Cond = X86::COND_B; // CF == 1 in rewriteArithmetic()
817 Cond = X86::COND_O; // OF == 1 in rewriteArithmetic()
827 unsigned &CondReg = CondRegs[Cond]; in rewriteArithmetic()
853 X86::CondCode Cond = X86::getCondFromCMov(CMovI); in rewriteCMov() local
921 X86::CondCode Cond = X86::getCondFromBranch(JmpI); in rewriteCondJmp() local
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/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp311 Cond.clear(); in analyzeBranch()
335 if (Cond.empty()) { in analyzeBranch()
376 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
382 assert(Cond.size() == 1); in analyzeBranch()
406 ArrayRef<MachineOperand> Cond, in insertBranch() argument
413 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
416 if (Cond.empty()) { in insertBranch()
426 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm(); in insertBranch()
476 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
477 assert(Cond.size() == 1 && "Invalid AVR branch condition!"); in reverseBranchCondition()
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/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFAdjustOpt.cpp242 auto *Cond = dyn_cast<ICmpInst>(BI->getCondition()); in serializeICMPCrossBB() local
243 if (!Cond || B2->getFirstNonPHI() != Cond) in serializeICMPCrossBB()
245 Value *B2Op0 = Cond->getOperand(0); in serializeICMPCrossBB()
246 auto Cond2Op = Cond->getPredicate(); in serializeICMPCrossBB()
252 Cond = dyn_cast<ICmpInst>(BI->getCondition()); in serializeICMPCrossBB()
253 if (!Cond) in serializeICMPCrossBB()
255 Value *B1Op0 = Cond->getOperand(0); in serializeICMPCrossBB()
256 auto Cond1Op = Cond->getPredicate(); in serializeICMPCrossBB()
277 PassThroughInfo Info(Cond, BI, 0); in serializeICMPCrossBB()
/llvm-project-15.0.7/llvm/test/Transforms/ADCE/
H A D2003-11-16-MissingPostDominanceInfo.ll8 br i1 %C, label %Cond, label %Done
10 Cond: ; preds = %0
13 Loop: ; preds = %Loop, %Cond
17 Done: ; preds = %Cond, %0
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DGuardUtils.cpp66 auto *Cond = BI->getCondition(); in parseWidenableBranch() local
67 if (!Cond->hasOneUse()) in parseWidenableBranch()
73 if (match(Cond, m_Intrinsic<Intrinsic::experimental_widenable_condition>())) { in parseWidenableBranch()
85 if (!match(Cond, m_And(m_Value(A), m_Value(B)))) in parseWidenableBranch()
87 auto *And = dyn_cast<Instruction>(Cond); in parseWidenableBranch()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUAsmUtils.h31 bool (*Cond)(T Context) = nullptr; member
40 bool (*Cond)(const MCSubtargetInfo &STI) = nullptr; member
52 return !Cond || Cond(STI); in isSupported()
/llvm-project-15.0.7/clang-tools-extra/pseudo/lib/
H A DDirectiveTree.cpp26 enum class Cond { None, If, Else, End }; enum in clang::pseudo::__anon141705870111::DirectiveParser
27 static Cond classifyDirective(tok::PPKeywordKind K) { in classifyDirective()
32 return Cond::If; in classifyDirective()
37 return Cond::Else; in classifyDirective()
39 return Cond::End; in classifyDirective()
41 return Cond::None; in classifyDirective()
77 Cond Kind = classifyDirective(Directive.Kind); in parse()
78 if (Kind == Cond::If) { in parse()
85 } else if ((Kind == Cond::Else || Kind == Cond::End) && !TopLevel) { in parse()
110 if (classifyDirective(Terminator->Kind) == Cond::End) { in parseConditional()
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/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dudiv_select_to_select_shift.ll5 ; udiv X, (Select Cond, C1, C2) --> Select Cond, (shr X, C1), (shr X, C2)
7 define i64 @test(i64 %X, i1 %Cond ) {
14 %divisor1 = select i1 %Cond, i64 16, i64 8
16 %divisor2 = select i1 %Cond, i64 8, i64 0

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