273                                  SmallVectorImpl<MachineOperand> &Cond,  in analyzeBranch()  argument
311       Cond.clear();  in analyzeBranch()
335     if (Cond.empty()) {  in analyzeBranch()
376       Cond.push_back(MachineOperand::CreateImm(BranchCode));  in analyzeBranch()
382     assert(Cond.size() == 1);  in analyzeBranch()
391     AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm();  in analyzeBranch()
406                                     ArrayRef<MachineOperand> Cond,  in insertBranch()  argument
413   assert((Cond.size() == 1 || Cond.size() == 0) &&  in insertBranch()
416   if (Cond.empty()) {  in insertBranch()
426   AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm();  in insertBranch()
476     SmallVectorImpl<MachineOperand> &Cond) const {  in reverseBranchCondition()
477   assert(Cond.size() == 1 && "Invalid AVR branch condition!");  in reverseBranchCondition()
479   AVRCC::CondCodes CC = static_cast<AVRCC::CondCodes>(Cond[0].getImm());  in reverseBranchCondition()
480   Cond[0].setImm(getOppositeCondition(CC));  in reverseBranchCondition()