Lines Matching refs:Cond
94 SmallVectorImpl<MachineOperand> &Cond) const { in AnalyzeCondBr()
101 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
104 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
110 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
113 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); in analyzeBranch()
120 ArrayRef<MachineOperand> Cond) const { in BuildCondBr()
121 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
125 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
126 assert((Cond[i].isImm() || Cond[i].isReg()) && in BuildCondBr()
128 MIB.add(Cond[i]); in BuildCondBr()
136 ArrayRef<MachineOperand> Cond, in insertBranch() argument
148 assert((Cond.size() <= 3) && in insertBranch()
153 BuildCondBr(MBB, TBB, DL, Cond); in insertBranch()
160 if (Cond.empty()) in insertBranch()
163 BuildCondBr(MBB, TBB, DL, Cond); in insertBranch()
196 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
197 assert( (Cond.size() && Cond.size() <= 3) && in reverseBranchCondition()
199 Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm())); in reverseBranchCondition()
205 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify, in analyzeBranch() argument
256 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond); in analyzeBranch()
285 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); in analyzeBranch()